CYC1000 User Guide
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January 2020
Board Reference
FPGA Pin No.
Description
I/O Standard
SEN_INT1
PIN_B1
Interrupt 1
3.3 V
SEN_INT2
PIN_C2
Interrupt 2
3.3 V
SEN_SDI
PIN_G2
Data In (MOSI)*
3.3 V
SEN_SDO
PIN_G1
Data Out (MISO)*
3.3 V
SEN_SPC
PIN_F3
Clock*
3.3 V
SEN_CS
PIN_D1
Chip Select*
3.3 V
*For SPI connection
3.3.4
SDRAM Memory
The CYC1000 board supports 64MBit (default version) or up to 256MBit (customized version)
SDRAM which can operate up to 166 MHz clock frequency. Below are the connections and pinning
of the SDRAM used in the CYCX1000.
Board Reference
FPGA Pin No.
Description
I/O Standard
A0
PIN_A3
SDRAM Address [0]
3.3 V
A1
PIN_B5
SDRAM Address [1]
3.3 V
A2
PIN_B4
SDRAM Address [2]
3.3 V
A3
PIN_B3
SDRAM Address [3]
3.3 V
A4
PIN_C3
SDRAM Address [4]
3.3 V
A5
PIN_D3
SDRAM Address [5]
3.3 V
A6
PIN_E6
SDRAM Address [6]
3.3 V
A7
PIN_E7
SDRAM Address [7]
3.3 V
A8
PIN_D6
SDRAM Address [8]
3.3 V
A9
PIN_D8
SDRAM Address [9]
3.3 V
A10
PIN_A5
SDRAM Address [10]
3.3 V
A11
PIN_E8
SDRAM Address [11]
3.3 V
A12
PIN_A2
SDRAM Address [12]
3.3 V
A13
PIN_C6
SDRAM Address [13]
3.3 V
BA0
PIN_A4
SDRAM Bank Address [0]
3.3 V
BA1
PIN_B6
SDRAM Bank Address [1]
3.3 V
RAS
PIN_B7
SDRAM Row Address Strobe
3.3 V
CAS
PIN_C8
SDRAM Column Address Strobe
3.3 V
WE
PIN_A7
SDRAM Write Enable
3.3 V
CS
PIN_A6
SDRAM Chip Select
3.3 V
Figure 8
–
SDRAM Connections
