3-4
All the MCF5206 internal registers, configuration registers, parallel I/O port registers, DUART registers
and system control registers are mapped by MBAR register at 1K-byte boundary. It is mapped to
$10000000 by dBUG. For complete map of these registers refer to the MCF5206 User's Manual.
The SBC5206 board can have up to 32M bytes of DRAM installed. The first 32M bytes are reserved for
this memory. Refer to Section 3.2 for a discussion of RAM. The dBUG is programmed in two 29F010
Flash ROM’s which only occupies 256K bytes of the address space. The first 128K bytes are used by
dBUG and the second half is left for user. Refer to section 3.3.
The MC68HC901 is used as dBUG serial communication, baud rate generator, and ISA Bus interrupt
request. Refer to section 3.4.2.
The ISA Bus interface maps all the I/O space of the ISA bus to the MCF5206 memory at address
$04000000. Refer to section 3.6.
TABLE 3.1. The SBC5206 memory map.
ADDRESS RANGE
SIGNAL and DEVICE
$00000000-$01FFFFFF1
-RAS1, -RAS2, Up to 32M bytes of DRAM’s.
$10000000-$100003FF
Internal Module registers
$20000000-$200001FF
Internal SRAM
$30000000-$300FFFFF
-CS2, 1M space for MC68HC901. -CS1 is used for IACK.
$40000000-$400FFFFF
-CS3, 1M ISA Bus area
$FFE00000-$FFE3FFFF
-CS0, 256K bytes of Flash ROM.
1 Refer to the text for more detail.
All the unused area of the memory map is available to the user.
3.1.9 Reset Vector Mapping
After reset, the processor attempts to get the initial stack pointer and initial program counter values from
locations $000000-$000007 (the first eight bytes of memory space). This requires the board to have a
nonvolatile memory device in this range with proper information. However, in some systems, it is
preferred to have RAM starting at address $00000000. In MCF5206, the -CS0 responds to any accesses
after reset until the CSMR0 is written. This includes the reset vector range. Since -CS0 is connected to
Flash ROM’s, the Flash ROM’s appear to be at address $00000000 which provides the initial stack
pointer and program counter (the first 8 bytes of the Flash ROM). The initialization routine, however,
programs the chip-select logic and locates the Flash ROM’s to start at $FFE00000 and the DRAM’s to
start at $00000000.
3.1.10 -TA Generation
The processor starts a bus cycle by providing the necessary information (address, R/-W, etc.) and
asserting the -TS. The processor then waits for an acknowledgment (-TA) by the addressed device before
it can complete the bus cycle. This -TA is used not only to indicate the presence of a device, it also
allows devices with different access time to communicate with the processor properly. The MCF5206, as
part of the chip-select logic, has a built in mechanism to generate the -TA for all external devices which
do not have the capability to generate the -TA on their own. The Flash ROM’s and DRAM’s can not
generate the -TA. Their chip-select logic’s are programmed by dBUG to generate the -TA internally after
a preprogrammed number of wait states. In order to support the future expansion of the board, the -TA
input of the processor is also connected to the Processor Expansion Bus, J9. This allows the expansion
boards to assert this line to indicate their -TA to the processor. On the expansion boards, however, this
signal should be generated through an open collector buffer with no pull-up resistor, a pull-up resistor is
included on the board. All the -TA’s from the expansion boards should be connected to this line.
3.1.11 Wait State Generator
