3-1
CHAPTER 3
HARDWARE DESCRIPTION AND RECONFIGURATION
This chapter provides a functional description of the SBC5206 board hardware. With the description
given here and the schematic diagram provided at the end of this manual, the user can gain a good
understanding of the board's design. In this manual, an active low signal is indicated by a "-" preceding
the signal name.
3.1 THE PROCESSOR AND SUPPORT LOGIC
This part of the Chapter discusses the CPU and general supporting logic on the SBC5206 board.
3.1.1 The Processor
The microprocessor used in the SBC5206 is the highly integrated MCF5206, 32-bit processor. The
MCF5206 uses a ColdFire processor as the core with 512 bytes of instruction cache, two UART channels,
two Timers, 512 bytes of SRAM, Motorola M-Bus Module supporting the I
2
C, one-byte wide parallel I/O
port, and the supporting integrated system logic. All the registers of the core processor are 32 bits wide
except for the Status Register (SR) which is 16 bits wide. This processor communicates with external
devices over a 32-bit wide data bus, D0-D31 with support for 8 and 16-bit ports. This chip can address
the entire 4 G Bytes of memory space using internal chip-select logic. However, it provides only 28
address lines, A0-A27. All the processor's signals are available at J7, J9, and J10 for off the board
expansion. Refer to section 3.7 for pin assignment.
The MCF5206 has an IEEE JTAG-compatible port and BDM port. These signals are available at J8. The
processor also has the logic to generate up to eight (8) chip selects, -CS0 to -CS8 and two banks of
DRAM’s.
3.1.2 The Reset Logic
The reset logic provides system initialization under two modes. Under system power-up and when the
RESET switch, S2 (red switch), is activated. The power-on generates the Master RESET by asserting the
-RSTI and -HIZ which causes total system reset. The RESET switch generates Normal Reset which
resets the entire processor except the DRAM controller.
U9 is used to produce active low power-on RESET signal which feeds the LSI2032 (U4) along with the
Push-button RESET. The U4 device generates the system reset (-RESET) and ISA bus RESET signals.
dBUG performs the following configurations of internal resources during the initialization. The
instruction cache is invalidated and disabled. The Vector Base Register, VBR, points to the Flash.
However, a copy of the exception table is made at address $00000000 in DRAM. To take over an
exception vector, the user places the address of the exception handler in the appropriate vector in the
vector table located at $00000000, and then points the VBR to $00000000.
The Software Watchdog Timer is disabled, Bus Monitor enabled, and internal timers are placed in a stop
condition. Interrupt controller registers initialized with unique interrupt level/priority pairs. The parallel
I/O port is configured for I/O.
3.1.3 The -HIZ Signal
The -HIZ signal is actively driven by the LSI2032 (U4). This Signal is available for monitor on J10.
However, this signal should not be driven by the user. If the user need to drive the -HIZ, it should be
