3-3
the ABORT switch is not capable of generating a vector in response to level seven interrupt acknowledge
from the processor, the debugger programs this request for autovector mode.
The MC68HC901 reports its interrupt request on -IRQ4 line which is set for Level 4, priority 2. It uses
the vectored mode for acknowledgment. The chip-select -CS1 is used to generate the -IACK signal for
MC68HC901. The MC68HC901 is programmed to generate vectors $F0 to $FF. This should not be
changed.
The -IRQ1 line of the MCF5206 is not used on this board. However, the -IRQ1 is programmed for Level
1 with priority 1 and autovector. The user may use this line for external interrupt request. Refer to
MCF5206 User’s Manual for more information about the interrupt controller.
3.1.7 Internal SRAM
The MCF5206 has 512 bytes of internal memory. This memory is mapped to $20000000 and is not used
by the dBUG. It is available to the user.
3.1.8 The MCF5206 Registers and Memory Map
The memory and I/O resources of the SBC5206 are divided into three groups, MCF5206 Internal,
External resources, and the ISA Bus address. All the I/O registers are memory mapped.
The MCF5206 has built in logic and up to eight chip-select pins (-CS0 to -CS7) which are used to enable
external memory and I/O devices. In addition there are two -RAS lines for DRAM’s. There are eighteen
(32) registers to specify the address range, type of access, and the method of -TA generation for each
chip-select and -RAS pins. These registers are programmed by dBUG to map the external memory and
I/O devices.
The SBC5206 uses chip-select zero (-CS0) to enable the EPROM/Flash ROM ( refer to Section 3.3.) The
SBC5206 uses -RAS1 and -RAS2 to enable the DRAM SIMM module (refer to Section 3.2), -CS2 for
enabling the MC68HC901, -CS1 for Interrupt acknowledge of MC68HC901, and -CS3 for ISA Bus I/O
space.
The chip-select signals -CS4, -CS5, -CS6, and -CS7 share their pins with address lines A24, A25, A26,
and A27 and the write-enable lines -WE3, -WE2, -WE1, and -WE0. The pins for -CS6 and -CS7 are
programmed as write enable line -WE1 and -WE0 respectively to support the on-board Flash ROM. The
pins for -CS4 and -CS5 are programmed as chip select lines.
The chip select mechanism of the MCF5206 allows the memory mapping to be defined based on the
memory space desired (User/Supervisor, Program/Data spaces).
