AVS-500 Series Machine Vision User Manual
63
Max Link Speed
[Auto]
PEG1 Slot Power Limit Value
75
PEG1 Slot Power Limit Scale
[1.0x]
PEG1 Slot Power Limit Number
2
PEG 0:1:2 Not Present
Enable Root Port
[Auto]
Max Link Speed
[Auto]
PEG2 Slot Power Limit Value
75
PEG2 Slot Power Limit Scale
[1.0x]
PEG2 Slot Power Limit Number
3
Program PCIe ASPM after opROM
[Disabled]
Program Static Phase1 Eq
[Enabled]
Gen3 Adaptive Software
Equalization
Always Attempt SW EQ
[Disabled]
Nimber of Presets to test
[Auto]
Allow PERST# GPIO Usage
[Enabled]
SW EQ Enable VOC
[Auto]
Jitter Dwell Time
3000
Jitter Error Target
2
VOC Dwell Time
10000
VOC Error Target
2
Generate BDAT PEG Margin Date
[Disabled]
PCIe Rx CEM Test Mode
[Disabled]
PCIe Spread Spectrum Clocking
[Enabled]
►
PEG Port Feature Configuration
Detect Non-Compliance Device
[Disabled]
►
Gen3 Root Port Preset value for each Lane
Lane 0
7
Lane 1
7
Lane 2
7
Lane 3
7
Lane 5
7
Lane 6
7