UG-1757
Rev. 0 | Page 3 of 17
EVALUATION BOARD HARDWARE
POWER SUPPLIES
The EVAL-AD5413SDZ requires a number of power supply
inputs for the AV
DD1
, AV
DD2
, AV
SS
, and V
LOGIC
pins on the
If there is only one positive rail available, connect the AV
DD2
pin
to the AV
DD1
pin via the AVDD1-AVDD2-SHRT link on the
EVAL-AD5413SDZ. Select the V
LOGIC
supply from the 3.3V_SDP
board or the V
LDO
pin, through the JP1 and
JP3 jumpers. See Table 1 for more link options and the default
link positions.
The EVAL-AD5413SDZ operates with a power supply range from
−33 V on AV
SS
to +33 V on AV
DD1
with a maximum voltage of
50 V between the two rails. AV
DD2
requires a voltage between
4.5 V and 33 V. In a typical operating condition, AV
DD2
= +5 V,
AV
DD1
= +24 V, and AV
SS
= −24 V.
SERIAL COMMUNICATION
board handles the communication to the EVAL-
AD5413SDZ via the PC. By default, the
board handles the
serial port interface (SPI) communication, controls the RESET pin
and the LDAC pin, and monitors the FAULT pin of the
The EVAL-AD5413SDZ can disconnect from the
board
and drive the digital signals from an external source by removing
the appropriate links on P2 (see Table 2). An option to tie the
RESET pin and the LDAC pin to high or low levels is available
through the S1 switch and the JP11 link.
DEVICE ADDRESS PINS
Use the device address pins (AD0 and AD1) in conjunction with
the device address bits within the SPI frame to determine which
device is addressed by the system controller. The AD0 pin
and the AD1 pin can be configured through the JP12 and JP14
links (see Table 1).
Table 1. EVAL-AD5413SDZ Link Option Functions
Link
Default Position
Function
AVDD1-
AVDD2-SHRT
Not inserted
Connects the AV
DD2
pin to the AV
DD1
pin.
JP1
Not inserted
Selects 3.3 V from the
as the source for V
LOGIC
pin.
JP2
Inserted
Selects the external reference, ADR-REF, as the input to REFIN.
JP3
Inserted
Selects 3.3 V from the V
LDO
pin of the
as the source for the V
LOGIC
pin.
JP4
Not inserted
Selects REFOUT as the input to REFIN.
JP5
Inserted
Powers ADR-REF from the AV
DD2
pin (the maximum supply for the
JP8
Inserted
Connects the VI
OUT
pin to the +V
SENSE
pin.
JP10
Inserted
Connects the –V
SENSE
pin to the RETURN signal on the EVAL-AD5413SDZ.
JP11 A
Position A connects the LDAC pin to the ground position. Position B connects the LDAC pin to the V
LOGIC
pin.
JP12
A
Position A connects the AD0 pin to the ground position. Position B connects the AD0 pin to the V
LOGIC
pin.
JP14
A
Position A connects the AD1 pin to the ground position. Position B connects the AD1 pin to the V
LOGIC
pin.
JP17
Not inserted
Connects the AV
SS
pin to the ground position pin for the unipolar supply option (current output only).
P2
Inserted
Provides options to disconnect from the
board and to drive digital signals from an external source.
S1 Up
In the up position, this link connects the RESET pin to the V
LOGIC
pin.
Middle
(default)
In the middle position (default), this link controls the RESET pin via the
Down
In the down position, this link connects the RESET pin to the ground position pin.
Table 2. Link Options for P2 Header
Pin No.
Position
Function
1, 2
Inserted
Connects the FAULT signal from the
board to the FAULT pin on the
Not
inserted
Disconnects the FAULT signal from the
3, 4
Inserted
Connects the RESET signal from the
board to the RESET pin on the
Not
inserted
Disconnects the RESET signal from the
5, 6
Inserted
Connects the LDAC signal from the
board to the LDAC pin on the
Not
inserted
Disconnects the LDAC signal from the
7, 8
Inserted
Connects the SCLK signal from the
Not inserted
Disconnects the SCLK signal from the
9, 10
Inserted
Connects the SDO signal from the
Not inserted
Disconnects the SDO signal from the
11, 12
Inserted
Connects the SDI signal from the
Not inserted
Disconnects the SDI signal from the
13, 14
Inserted
Connects the SYNC signal from the
board to the SYNC pin on the
Not
inserted
Disconnects the SYNC signal from the