Analog Devices Blackfin, Getting Started

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What are Blackfin Processors?
1-6 Getting Started With Blackfin Processors
An exception is generated whenever unauthorized access is made to a pro-
tected area of memory. The kernel services this exception and takes
appropriate action.
The high processing speeds achieved by Blackfin processors translate into
several tangible benefits. The first is time to market. There can be consid-
erable savings in reducing or bypassing the code optimization effort when
there is plenty of processing capacity to spare. A second benefit is reduced
software maintenance, which can otherwise dominate a product’s life cycle
cost. Finally, for scalable Blackfin architectures, designers can base their
work around the most capable member of the Blackfin processor family,
and can use a cost-optimized processor.
Dual-Core Processors Add Flexibility
Blackfin processors are also available as dual-core devices. The traditional
use of a dual-core processor employs discrete and often different tasks that
run on each of the cores. For example, one core might perform all of the
control-related tasks, such as graphics and overlay functionality, network-
ing, interfacing to bulk storage, and overall flow control. This core is also
where the operating system or kernel most likely resides. Meanwhile, the
second core is dedicated to the application’s high-intensity processing
functions. For example, compressed data packets might be transferred
over a network interface to the first core for preprocessing, and then
passed to the second core for audio and video decoding.
Figure 1-2 shows
a block diagram of a typical dual-core processor.
The use of a dual-core processor is preferred for designs built by separate
software development teams. The ability to segment these types of func-
tions allows a parallel design process, eliminating critical path
dependencies in the project. This programming model also aids the testing
and validation phases of the project. For example, a code change on one
core does not necessarily invalidate the testing efforts already completed
on the other core.