Analog Devices Blackfin, Getting Started

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Getting Started With Blackfin Processors 1-23
Introduction
At the core, Blackfin processors have a 16-bit, dual MAC (multiply/accu-
mulate) architecture with 32-bit registers and 64-bit internal data paths.
This core is surrounded by high-speed memory and high-speed peripherals
including 100 Mbps serial ports (SPORTs), a high-speed parallel periph-
eral interface (PPI) capable of moving digital video-on and off chip
(ITU-R/CCIR-656 compliant), UART with IrDA
®
support, SPI port,
and an external memory interface for connection to SDRAM or DDR
SDRAM, flash, SRAM, and so on.
In addition to its advanced peripherals, Blackfin processors include an
on-chip switching regulator and a software-programmable on-chip phase
lock loop (PLL) that allows software to control the core clock speed and
core voltage. This can result in huge power savings because the clock and
voltage can be constantly varied, depending on the task at hand.
Since Blackfin processors can be used for both control/data processing and
signal processing, the efficiency of data movement and storage has a high
impact on performance. Efficient numerical precision is important,
although efficiency of data movement is equally as important. The mea-
sured width of a signal processing device is often based on the type of data
it processes most efficiently. The width of a processor is typically mea-
sured by its data paths and register widths. Blackfin processors support 8-,
16-, and 32-bit arithmetic operations in hardware, but are optimized for
(and have the most support for) 16-bit operations. Thus, Blackfin proces-
sors are considered to be 16/32-bit processors.
Performance
Processors can no longer be judged solely on core clock speed, MHz,
MIPS, MACS, FLOPS, and so on. Newer Blackfin processors run at core
clock frequencies starting at 300 MHz. Their internal memory is L1,
which means that memory also runs at the core clock rate, providing large
amounts of bandwidth between a processor’s core and its internal mem-
ory. The core supports two 16-bit multiply/accumulates per cycle
sustained, providing 1.2 GMACs at 600 MHz.