Evaluation Board User Guide
UG-500
Rev. 0 | Page 11 of 15
SCHEMATIC DIAGRAM
DTEST
47 uF Capacitors Not Assembled
PADs Placed on Bottom Side
R14
1k5
R10
0R
TP15
1
TP8
1
R8
1k5
J6
J7
R15
1k5
C8
47u
TP6
1
R13
1k5
R18
150m
J9
SN11
J8
J3
CON3
1
2
3
C1
1u
TP7
1
TP14
1
TP16
1
U3A
SY M 1 OF 1
pca9557dbg4
P1
7
P0
6
A2
5
A1
4
A0
3
GND
8
SCL
1
VCC
16
RESET*
15
SDA
2
P7
14
P6
13
P5
12
P4
11
P3
10
P2
9
D1
LED
C4
22uF
TP18
1
J1
CON4
1
2
3
4
TP19
1
C9
47u
TP12
1
R17
470R
U1
adp1720
ADJ
1
VIN
2
VOUT
3
EN
4
GND5
5
GND6
6
GND7
7
GND8
8
JP2
HeaderLarge10x2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
TP17
1
J11
CON3
1
2
3
C10
47u
JP1
HEADER_3
1
1
2
2
3
3
C7
47u
J5
TP10
1
J10
J2
CON4
1
2
3
4
TP5
1
R7
N.A.
R2
100k
C11
47u
R6
N.A.
C5
22uF
TP11
1
SN3
JP3
HeaderLarge10x2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
R16
0R
TP20
1
C2
1u
R5
N.A.
C6
100n
TP13
1
R1
56k
TP9
1
R11
0R
ISO_B_S
ISO_B_F
SY S_EN
BAT_SNS
SDA
ISO_S_S
SCL
AGND
AGND
ISO_S_F
VIN_F
ISO_B_S
ISO_B_F
VIN_S
DIG_IO1_S
ISO_S_F
ISO_S_S
DIG_IO2_S
SDA
SCL
SCL
DIG_IO1
SDA
DIG_IO2
THR
BAT_SNS
SY S_EN
SY S_EN
VDD_LDO
VI
N
_
F
IS
O
_
B
_
F
IS
O
_
S
_
F
Connectors to motherboard
DIG_IO1_S
DIG_IO2
DIG_IO1
ATEST1
SN8
DIG_IO3
DIG_IO2_S
DIG_IO3_S
DIG_IO3
DIG_IO3_S
ILED_S
ILED
ILED_S
ILED
VIN_F
BAT
_
S
N
S
TH
R
VDDIO
ISO_S_F
ISO_S_F
VDDIO
VDDIO
ISO_S_F
ILED
SN4
SN5
ATEST2
ATEST3
ATEST4
R3
U2
ADP5062 QFN20
SCL
1
DIG_IO3
2
DIG_IO2
3
BAT_SNS
4
DIG_IO1
5
VIN1
6
ISO_B2
13
VIN3
8
ISO_S1
9
ISO_S2
10
ISO_S3
11
ISO_B1
12
CB
P
19
AG
N
D
20
ILED
15
SY S_EN
16
SDA
17
THR
18
VIN2
7
ISO_B3
14
PD
PAD
C12
100nF
SN10
SN6
CBP
TP3
1
TP2
1
TP4
1
TP1
1
C3
10uF
SCL
CBP_S
VIN_S
VIN_F
BAT_SNS
SDA
Figure 7.
ADP5062
LFCSP Demo Board Schematic
