Chapter 3
Hardware
32 Reference
Manual
LittleBoard
800
Pin #
Signal
Descriptions (J1 Row C)
5 (C4)
LA21
Latchable Address 21 – Refer to pin-C2, for more information.
6 (C5)
LA20
Latchable Address 20 – Refer to pin-C2, for more information.
7 (C6)
LA19
Latchable Address 19 – Refer to pin-C2, for more information.
8 (C7)
LA18
Latchable Address 18 – Refer to pin-C2, for more information.
9 (C8)
LA17
Latchable Address 17 – Refer to pin-C2, for more information.
10 (C9)
MEMR*
Memory Read – This signal instructs a selected memory device to drive
data onto the data bus. It is active on all memory read cycles.
11 (C10)
MEMW*
Memory Write – This signal instructs a selected memory device to store
data currently on the data bus. It is active on all memory write cycles.
12 (C11)
SD8
System Data 8 – Refer to pin-A2 for more information.
13 (C12)
SD9
System Data 9 – Refer to pin-A2 for more information.
14 (C13)
SD10
System Data 10 – Refer to pin-A2 for more information.
15 (C14)
SD11
System Data 11 – Refer to pin-A2 for more information.
16 (C15)
SD12
System Data 12 – Refer to pin-A2 for more information.
17 (C16)
SD13
System Data 13 – Refer to pin-A2 for more information.
18 (C17)
SD14
System Data 14 – Refer to pin-A2 for more information.
19 (C18)
SD15
System Data 15 – Refer to pin-A2 for more information.
20 (C19)
NC
Not connected
Notes:
The shaded area denotes power or ground. The signals marked with * = Negative true logic.
Table 3-8. PC/104 Interface Pin/Signal Descriptions (J1D)
Pin #
Signal
Descriptions (J1 Row D)
21 (D0)
GND
Ground
22 (D1)
MEMCS16* Memory Chip Select 16 – This is signal is driven low by a memory slave
device to indicates it is cable of performing a 16-bit memory data transfer.
This signal is driven from a decode of the LA23 to LA17 address lines.
23 (D2)
IOCS16*
I/O Chip Select 16 – This signal is driven low by an I/O slave device to
indicate it is capable of performing a 16-bit I/O data transfer. This signal is
driven from a decode of the SA15 to SA0 address lines.
24 (D3)
IRQ10
Interrupt Request 10 – Asserted by a device when it has pending interrupt
request. Only one device may use this request line at a time.
25 (D4)
IRQ11
Interrupt Request 11 – Asserted by a device when it has pending interrupt
request. Only one device may use this request line at a time.
26 (D5)
IRQ12
Interrupt Request 12 – Asserted by a device when it has pending interrupt
request. Only one device may use this request line at a time.
27 (D6)
IRQ15
Interrupt Request 15 – Asserted by a device when it has pending interrupt
request. Only one device may use this request line at a time.
28 (D7)
IRQ14
Interrupt Request 14 – Asserted by a device when it has pending interrupt
request. Only one device may use this request line at a time.
29 (D8)
DACK0*
DMA Acknowledge 0 – Used by DMA controller to select the I/O resource
requesting the bus, or to request ownership of the bus as a bus master
device. Can also be used by the ISA bus master to gain control of the bus
from the DMA controller.
30 (D9)
DRQ0
DMA Request 0 – Used by I/O resources to request DMA service. Must be
held high until associated DACK0 line is active.
Summary of Contents for LittleBoard 800
Page 1: ...LittleBoard 800 Single Board Computer Reference Manual P N 5001743A Revision A...
Page 26: ...Chapter 2 Product Overview 20 Reference Manual LittleBoard 800...
Page 82: ...Chapter 4 BIOS Setup 76 Reference Manual LittleBoard 800...
Page 84: ...Appendix A Technical Support 78 Reference Manual LittleBoard 800...
Page 90: ...Appendix C Connector Part Numbers 84 Reference Manual LittleBoard 800...
Page 94: ...Index LittleBoard 800 Reference Manual 88...
Page 95: ......
Page 96: ......
