Ampro LittleBoard 800, Reference Manual

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Chapter 3 Hardware
LittleBoard 800 Reference Manual 25
PC/104-Plus Interface (J2)
PC/104- Plus uses a 120 pin (4x30) 2mm connector interface. This interface connector carries all of the
appropriate PCI signals operating at clock speeds up to 33MHz. The Memory Hub (82855GME),
integrates a PCI arbiter that supports up to four devices with three external PCI masters. This interface
header accepts stackable modules and is located on the top of the board.
Table 3-4 provides the signals and descriptions for the PCI bus pin-outs of 120 pins, 4 rows, consecutive
numbering, (A1, B1, C1, D1), 2mm connector.
Table 3-4. PC/104-Plus Pin/Signal Descriptions (J2)
Pin # Signal Input/
Output Description
1 (A1) Key/GND Key – Ground
2 (A2) VI/O +5 volts ±5% (Reference voltage only)
3 (A3) AD05 T/S
PCI Address/Data Bus Line 5 – These signals (AD31 - AD0) are
multiplexed on these pins. A bus transaction consists of an address
followed by one or more data cycles.
4 (A4) C/BE0* T/S PCI Bus Command/Byte Enable 0 – These signals (C/BE 0 -3) are
line multiplexed, so that during the address cycle, the command is
defined and during the data cycle, the byte enable is defined.
5 (A5) GND Ground
6 (A6) AD11 T/S Address/Data Bus Line 11 – Refer to pin-A3 for more information.
7 (A7) AD14 T/S Address/Data Bus Line 14 – Refer to pin-A3 for more information.
8 (A8) +3.3V +3.3 volts ±5% power supply input
9 (A9) SERR* O/D System Error – This signal is for reporting address parity errors.
10 (A10) GND Ground
11 (A11) STOP* S/T/S Stop – This signal indicates the current selected device is requesting
the master to stop the current transaction
12 (A12) +3.3V +3.3 volts ±5% power supply input
13 (A13) FRAME* S/T/S Frame access – This signal is driven by the current master, indicating
a transaction start and will remain active until the final data cycle.
14 (A14) GND Ground
15 (A15) AD18 T/S Address/Data Bus Line 18 – Refer to pin-A3 for more information.
16 (A16) AD21 T/S Address/Data Bus Line 21 – Refer to pin-A3 for more information.
17 (A17) +3.3V +3.3 volts ±5% power supply input
18 (A18) IDSEL0 In Initialization Device Select 0 – These signals (IDSEL 0-3) are used as
the chip-selects during configuration read and write transactions.
19 (A19) AD24 T/S Address/Data Bus Line 24 – Refer to pin A3 for more information.
20 (A20) GND Ground
21 (A21) AD29 T/S Address/Data Bus Line 29 – Refer to pin A3 for more information.
22 (A22) +5V +5 volts ±5% power supply input
23 (A23) REQ0* T/S Bus Request 0 – These signals (REQ 0-2) indicate to the arbitrator
the device desires use of the bus.
24 (A24) GND Ground