American Megatrends Baby Voyager 80486, User Manual

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Chapter 4 - AMIBIOS Features
56
ADVANCED CHIPSET SETUP Options
8-bit AT Cycle Wait State
This option sets the number of wait states inserted before 8-bit AT
cycle operations. The settings are 4 WS (the default) or 5 WS.
16-bit AT Cycle Wait State
This option sets the number of wait states inserted before 16-bit AT
cycle operations. The settings are 1 WS (the default) or 2 WS.
Cache Write Back
The settings are Enabled or Disabled (the default). If enabled, a
write-back caching algorithm is used. If disabled, a write-through
caching algorithm is used.
Non-Cacheable Block-1
This option selects the allocation method used for Non-Cacheable
Block 1. The settings are DRAM (local DRAM is used - the default)
or ATBus (DRAM is disabled and the AT bus is used).
Non-Cacheable Block-1 Size
If the Non-Cacheable Block Base Address setting is 512 KB, the
block size settings are 128 KB or Disabled (the default). If the
Non-
Cacheable Block-1 Base Address
setting is any other value, the
settings are 64KB, 128KB, 256KB, 512KB, 1MB, 2MB, 4MB, or
Disabled.
Non-Cacheable Block-1 Base
The Non-Cacheable Block-1 Base Address can change in
increments equal to the setting of
Non-Cacheable Block-1 Size
. If
below 1 MB, the Non-Cacheable Block-1 Base Address can only be
512KB (the default).