AMD Geode™ SC3200 Processor Data Book
199
Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0
32581C
Index 70h-71h
IOCS1# Base Address Register (R/W)
Reset Value: 0000h
15:0
I/O Chip Select 1 Base Address.
This 16-bit value represents the I/O base address used to enable assertion of IOCS1#
(ball D10 or N30 - see PMR[23] in Table 4-2 on page 70).
This register is used in conjunction with F0 Index 72h (IOCS1# Control register).
Index 72h
IOCS1# Control Register (R/W)
Reset Value: 00h
This register is used in conjunction with F0 Index 70h (IOCS1# Base Address register).
7
I/O Chip Select 1 Positive Decode (IOCS1#).
0: Disable.
1: Enable.
6
Writes Result in Chip Select.
When this bit is set to 1, writes to configured I/O address (base address configured in F0
Index 70h; range configured in bits [4:0]) cause IOCS1# to be asserted.
0: Disable.
1: Enable.
5
Reads Result in Chip Select.
When this bit is set to 1, reads from configured I/O address (base address configured in F0
Index 70h; range configured in bits [4:0]) cause IOCS1# to be asserted.
0: Disable.
1: Enable.
4:0
IOCS1# I/O Address Range.
This 5-bit field is used to select the range of IOCS1#.
00000: 1 Byte
01111: 16 Bytes
00001: 2 Bytes
11111: 32 Bytes
00011: 4 Bytes
All other combinations are reserved.
00111: 8 Bytes
Index 73h
Reserved
Reset Value: 00h
Index 74h-75h
IOCS0# Base Address Register (R/W)
Reset Value: 0000h
15:0
I/O Chip Select 0 Base Address.
This 16-bit value represents the I/O base address used to enable the assertion of
IOCS0# (ball A10 - see PMR[23] in Table 4-2 on page 70).
This register is used in conjunction with F0 Index 76h (IOCS0# Control register).
Index 76h
IOCS0# Control Register (R/W)
Reset Value: 00h
This register is used in conjunction with F0 Index 74h (IOCS0# Base Address register).
7
I/O Chip Select 0 Positive Decode (IOCS0#).
0: Disable.
1: Enable.
6
Writes Result in Chip Select.
When this bit is set to 1, writes to configured I/O address (base address configured in F0
Index 74h; range configured in bits [4:0]) cause IOCS0# to be asserted.
0: Disable.
1: Enable.
5
Reads Result in Chip Select.
When this bit is set to 1, reads from configured I/O address (base address configured in F0
Index 74h; range configured in bits [4:0]) cause IOCS0# to be asserted.
0: Disable.
1: Enable.
4:0
IOCS0# I/O Address Range.
This 5-bit field is used to select the range of IOCS0#.
00000: 1 Byte
01111: 16 Bytes
00001: 2 Bytes
11111: 32 Bytes
00011: 4 Bytes
All other combinations are reserved.
00111: 8 Bytes
Index 77h
Reserved
Reset Value: 00h
Table 6-29. F0: PCI Header/Bridge Configuration Registers for GPIO and LPC Support (Continued)
Bit
Description
Summary of Contents for Geode SC3200
Page 8: ...8 AMD Geode SC3200 Processor Data Book List of Figures 32581C...
Page 16: ...16 AMD Geode SC3200 Processor Data Book Overview 32581C...
Page 24: ...24 AMD Geode SC3200 Processor Data Book Architecture Overview 32581C...
Page 350: ...350 AMD Geode SC3200 Processor Data Book Debugging and Monitoring 32581C...
Page 420: ...420 AMD Geode SC3200 Processor Data Book Electrical Specifications 32581C...