178
AMD Geode™ SC3200 Processor Data Book
Core Logic Module - Register Summary
32581C
Table 6-17. F1: PCI Header Registers for SMI Status and ACPI Support Summary
F1 Index
Width
(Bits)
Type
Name
Reset
Value
Reference
(Table 6-32)
00h-01h
16
RO
Vendor Identification Register
100Bh
Page 234
02h-03h
16
RO
Device Identification Register
0501h
Page 234
04h-05h
16
R/W
PCI Command Register
0000h
Page 234
06h-07h
16
RO
PCI Status Register
0280h
Page 234
08h
8
RO
Device Revision ID Register
00h
Page 234
09h-0Bh
24
RO
PCI Class Code Register
068000h
Page 234
0Ch
8
RO
PCI Cache Line Size Register
00h
Page 234
0Dh
8
RO
PCI Latency Timer Register
00h
Page 234
0Eh
8
RO
PCI Header Type Register
00h
Page 234
0Fh
8
RO
PCI BIST Register
00h
Page 234
10h-13h
32
R/W
Base Address Register 0 (F1BAR0) — Sets the base address for
the I/O mapped SMI Status Registers (summarized in Table 6-18).
00000001h
Page 234
14h-2Bh
---
---
Reserved
00h
Page 234
2Ch-2Dh
16
RO
Subsystem Vendor ID
100Bh
Page 234
2Eh-2Fh
16
RO
Subsystem ID
0501h
Page 234
30h-3Fh
---
---
Reserved
00h
Page 234
40h-43h
32
R/W
Base Address Register 1 (F1BAR1) — Sets the base address for
the I/O mapped ACPI Support Registers (summarized in Table 6-
19)
00000001h
Page 234
44h-FFh
---
---
Reserved
00h
Page 234
Table 6-18. F1BAR0: SMI Status Registers Summary
I/O Offset
Width
(Bits)
Type
Name
Reset
Value
Reference
(Table 6-33)
00h-01h
16
RO
Top Level PME/SMI Status Mirror Register
0000h
Page 235
02h-03h
16
RO/RC
Top Level PME/SMI Status Register
0000h
Page 236
04h-05h
16
RO
Second Level General Traps & Timers PME/SMI Status Mirror
Register
0000h
Page 238
06h-07h
16
RC
Second Level General Traps & Timers PME/SMI Status Register
0000h
Page 239
08h-09h
16
Read to
Enable
SMI Speedup Disable Register
0000h
Page 240
0Ah-1Bh
---
---
Reserved
00h
Page 240
1Ch-1Fh
32
RO
ACPI Timer Register
xxxxxxxxh
Page 240
20h-21h
16
RO
Second Level ACPI PME/SMI Status Mirror Register
0000h
Page 240
22h-23h
16
RC
Second Level ACPI PME/SMI Status Register
0000h
Page 241
24h-27h
32
R/W
External SMI Register
00000000h
Page 241
28h-4Fh
---
---
Not Used
00h
Page 244
50h-FFh
---
---
The I/O mapped registers located here (I/O Offset 50h-FFh) are also accessible at F0
Index 50h-FFh. The preferred method is to program these registers through the F0 register space.
Summary of Contents for Geode SC3200
Page 8: ...8 AMD Geode SC3200 Processor Data Book List of Figures 32581C...
Page 16: ...16 AMD Geode SC3200 Processor Data Book Overview 32581C...
Page 24: ...24 AMD Geode SC3200 Processor Data Book Architecture Overview 32581C...
Page 350: ...350 AMD Geode SC3200 Processor Data Book Debugging and Monitoring 32581C...
Page 420: ...420 AMD Geode SC3200 Processor Data Book Electrical Specifications 32581C...