General Circuit Interface (GCI)
Am186™CC/CH/CU Microcontrollers User’s Manual
17-19
bus by setting all remaining TIC bus address bits to 1. (This assures that the lowest
address has priority. If the remaining bits are not immediately set to 1, addresses such
as 101 and 011 would have equal priority.) If a bit is overwritten and an address mismatch
occurs, the TIC bus controller returns to step 2.
5. If access was granted, the C/I0 channel is in possession of the GCI TIC bus, and C/I0
communication can begin in the following GCI frame.
Note: When GCI TIC access is granted, BAC = 0—regardless of S/G. At this point, both
C/I0 and the HDLC controller have access to the GCI TIC bus (i.e., if the HDLC controller
needs to transmit D-channel data, it does not have to arbitrate for the GCI TIC bus—TIC
bus access has already been established). The HDLC controller does not have to arbitrate
for the GCI TIC bus, but it must wait for an asserted S/G from the transceiver before it
receives its internal CTS and can transmit, as stated in the previous section. To relinquish
the GCI TIC bus after a C/I0 or D-channel transmission, both the C/I0 request (a software
request) and the HDLC controller request (a hardware request) must be deasserted. When
the software request bit has been cleared (ending C/I0 transmission), the C/I0 channel is
not allowed back onto the same established TIC bus should it remain open for a HDLC
transmission. When the TIC bus is given up by the HDLC controller, neither the D-channel
nor the C/I0 channel is allowed access to the TIC bus again for at least one GCI frame.
6. After the completion of C/I0 data, software should remove its request by clearing its
request bit. When done, the C/I0 channel control is withdrawn from the TIC bus (BAC
is set back to 1 in the following frame as long as the HDLC controller has no D-channel
communication in progress) and the C/I0 channel is prevented from accessing the TIC
bus again for one GCI frame (i.e., the channel is moved into a lower priority as mentioned
earlier in this chapter). This gives all connected devices an equal chance to access the
TIC bus.
17.5.7.6
IC Channel Operation
The two IC channels have access to a single interrupt-driven microprocessor
transmit/receive buffer. A register bit determines which channel gets access to this buffer.
Because the data output is open-drain, the unused IC channel and all High bits of the
chosen IC channel are placed in a high-impedance state (unless driven by an HDLC channel
through a Time Slot Assigner).
17.5.8
Interrupts
The GCI controller can generate the following maskable interrupts (sharing one direct
processor interrupt line) using the GISTAT and GIMSK registers.
■
IC Buffer Available or Buffer Empty: Indicates that a byte of data has been received
on the IC channel, and that a new IC byte can be loaded for transmission.
■
GCI Timing Request: Response to GCI_DCL_A starting (going High) from the
deactivated state.
■
Change in C/I1 Channel Status: Indicates that the contents on the receive side of
C/I channel 1 have changed since the C/I Receive Data register was last read.
■
Change in C/I0 Channel Status: Indicates that the contents on the receive side of
C/I channel 0 have changed since the C/I Receive Data register was last read.
■
Monitor Channel Receive Abort Detected: Indicates an implied transmitter abort due
to out-of-sequence transmit handshake bits or handshake bit transmission errors.
■
Monitor Channel Collision Detected: Indicates that a collision has occurred on the
monitor channel during the transmission of a monitor byte.
Summary of Contents for Am186 CC
Page 1: ...Am186 CC CH CU Microcontrollers User s Manual Order 21914B...
Page 4: ...iv Am186 CC CH CU Microcontrollers User s Manual...
Page 18: ...Table of Contents xviii Am186 CC CH CU Microcontrollers User s Manual...
Page 24: ...Introduction xxiv Am186 CC CH CU Microcontrollers User s Manual...
Page 40: ...Architectural Overview 1 16 Am186 CC CH CU Microcontrollers User s Manual...
Page 86: ...System Overview 3 36 Am186 CC CH CU Microcontrollers User s Manual...
Page 92: ...Emulator Support 4 6 Am186 CC CH CU Microcontrollers User s Manual...
Page 112: ...DRAM Controller 6 8 Am186 CC CH CU Microcontrollers User s Manual...
Page 134: ...Interrupts 7 22 Am186 CC CH CU Microcontrollers User s Manual...
Page 186: ...Programmable I O Signals 9 8 Am186 CC CH CU Microcontrollers User s Manual...
Page 200: ...Watchdog Timer 11 6 Am186 CC CH CU Microcontrollers User s Manual...
Page 232: ...Asynchronous Serial Ports UARTs 13 24 Am186 CC CH CU Microcontrollers User s Manual...
Page 242: ...Synchronous Serial Port SSI 14 10 Am186 CC CH CU Microcontrollers User s Manual...
Page 264: ...High Level Data Link Control HDLC 15 22 Am186 CC CH CU Microcontrollers User s Manual...
Page 332: ...Universal Serial Bus USB 18 34 Am186 CC CH CU Microcontrollers User s Manual...
Page 348: ...Register Summary A 16 Am186 CC CH CU Microcontrollers User s Manual...
Page 376: ...Index Index 18 Am186 CC CH CU Microcontrollers User s Manual...