ADM-XRC-9R1 User Manual
V1.7 - 16th Sept 2020
3.7 RF Interfaces
3.7.1 Front-Panel I/O
The front panel interface consists of a 20-way high-speed connector J2. This connector Supports an external
reference clock input and output, two GPIO pins, 8 DAC signals and 8 ADC signals. The connector part number
is Nicomatic CMM342D000F51-0020-240002.
Figure 14 : Front Panel IO
The GPIO signals are buffered through level translators, with direction controlled by FPGA pin A13 for EXTIO0
and FPGA pin A12 for EXTIO1. The direction pin should be low for input, high for output. There is a pull-down
resistor to ensure the GPIO signals are input by default. These level translators will provide some ESD/over
voltage protection to the FPGA inputs, and have a maximum data rate of 210Mbps.
The DACs and ADCs use a MiniCircuits TCM2-43X+ 10-4000MHz transformer to convert the 100Ohm differential
signal to 50Ohm single ended. It is also possible to fit a TCM2-672X+ 1700-6700MHz transformer.
The default configuration for the DAC is to operate in 20mA mode, with 2.5V DAC_AVTT). It is possible to run in
32mA mode, with 3.3V DAC_AVTT. Please contact Alpha Data for further details if this is required.
The ADC voltages in the table below are the single ended voltages at the RF connector. The DAC voltages are
the voltages driving a 50 Ohm impedance.
Signal
Impedance (Ohms)
J2 pin number
ADC0
50
20
ADC1
50
19
ADC2
50
18
ADC3
50
17
ADC4
50
16
ADC5
50
15
ADC6
50
14
ADC7
50
13
DAC0
50
10
Table 18 : Front panel I/O signals (continued on next page)
Page 20
Functional Description
ad-ug-1353_v1_7.pdf
