ADM-XRC-9R1 User Manual
V1.7 - 16th Sept 2020
3.6.3 Memory Interfaces
The ADM-XRC-9R1 has two independent banks of DDR4 SDRAM. Each bank consists of one 8-bit wide
memory device capable of running at up to 1200MHz (DDR-2400). 8Gbit devices (Micron MT40A1G8PM-083E)
are fitted as standard.
The memory banks are arranged for compatibility with the Xilinx Memory Interface Generator (MIG).
shows the component references and FPGA banks used. Full details of the interface, signaling standards
and an example design are provided in the ADM-XRC-9R1 example design.
Zynq RFSoC PL
Bank
66
DRAM Bank 1
U36
DRAM Bank 0
U37
300MHz
REFCLK
Bank
65
Bank 65
Bank 66
Figure 12 : PL DRAM Banks
3.6.4 GPIO
There are 19 GPIO pins from the FPGA, which are compatible with 3.3V signaling such as TTL and CMOS.
These GPIO pins are passed through a Texas Instruments TXS0108E level translator, capable of open-drain and
push-pull level translation. The level translator is auto direction sensing. The level translator has a propagation
delay of 5.7ns max and a channel-to-channel skew (within a package) of 1ns. Therefore, it is only suitable for
rates up to ~50Mb/s.
The GPIO pin mapping is shown in
.
PL
Bank 89
GPIO
Level Converter
P6
16 GPIO
PL
Bank 88
3 GPIO
Figure 13 : GPIO Block Diagram
Page 19
Functional Description
ad-ug-1353_v1_7.pdf
