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ADM-XRC-7Z2 User Manual
V1.2 - 24th Feb 2020

4.1.2 LED Definitions

There are seven LEDs to provide a visual indication of the board status.

Their locations are shown in 

Figure 3

Figure 3 : LED Locations

Comp. Ref.

Function

ON State

Off State

D5 (Green)

System Monitor
Status

See 

Table 19

 

D6 (Red)

System Monitor
Status

See 

Table 19

 

D8 (Green)

FPGA (PL)
Done

PL is configured

PL is not configured

D9 (Green)

Flash Boot
Enable

Enable PS booting PL from flash

Disable PS booting PL from flash

D10 (Amber)

MVMRO

Enable writes to non-volatile memories Inhibit writes to non-volatile memories

D11 (Red)

Power Good

Power Supplies off or faulty

Power Supplies operating correctly

D12 (Green)

System Reset

PS is in Reset

PS is not in Reset

Table 6 : Main LED Definitions

Page 7

Functional Description
ad-ug-1273_v1_2.pdf

Summary of Contents for ADM-XRC-7Z2

Page 1: ...ADM XRC 7Z2 User Manual Document Revision 1 2 24th Feb 2020...

Page 2: ...form without prior written consent from Alpha Data Parallel Systems Ltd Head Office Address Suite L4A 160 Dundee Street Edinburgh EH11 1DQ UK Telephone 44 131 558 2600 Fax 44 131 558 2700 email sales...

Page 3: ...P5 8 4 2 1 XMC Platform Interface 8 4 2 1 1 IPMI I2C 8 4 2 1 2 MBIST 8 4 2 1 3 MVMRO 8 4 2 1 4 MRSTI 8 4 2 1 5 MRSTO 8 4 2 1 6 MPRESENT 9 4 2 1 7 JTAG 9 4 2 2 P5 HSSIO Links 9 4 3 Secondary XMC Connec...

Page 4: ...le 6 Main LED Definitions 7 Table 7 Ethernet LED Definitions 8 Table 8 PCIEREFCLK Connections 10 Table 9 MGTCLK250M Connections 10 Table 10 PROGCLK Connections 10 Table 11 REFCLK200M Connections 11 Ta...

Page 5: ...connector Commercial Spec Option Programmable Logic PL Block consisting of 2 banks of DDR3 SDRAM 256MB per bank Ethernet interface to rear panel P6 connector Serial COM port connection to rear P6 con...

Page 6: ...C VITA 42 Connectors X2 XMC2 VITA 61 Connectors Table 1 Build Options 1 4 References Specifications ANSI VITA 42 0 XMC Standard December 2008 VITA ISBN 1 885731 49 3 ANSI VITA 42 3 XMC PCI Express Pro...

Page 7: ...mportant to check compatibility prior to installation If in doubt please contact Alpha Data for assistance IMPORTANT It is important to check compatibility with the carrier card prior to installation...

Page 8: ...observe ESD precautions Always wear a wrist strap when handling the card Hold the board by the edges Avoid touching any components Store in ESD safe bag 3 2 2 Installation in ADC XMC Breakout Carrier...

Page 9: ...Ref Clocks Power Supplies 7 0 GTX Transceivers VPWR 5V or 12V I2 C 3 3V PCIE RefClk PCIE HSSIO 7 0 P5 P6 P6 RefClk P6 PHY PHY PHY MAGS ETH1 ETH0 USB1 COM1 RS 232 COM2 RS 232 USB2 PHY DDR3 SDRAM 512MB...

Page 10: ...En Exclude BU67301 from JTAG chain Include BU67301 in JTAG chain Table 4 Switch 1 Definitions Switch 1 Ref Function OFF State ON State SW2 1 BootSel 0 See Table 15 SW2 2 BootSel 1 See Table 15 SW2 3...

Page 11: ...Monitor Status See Table 19 D8 Green FPGA PL Done PL is configured PL is not configured D9 Green Flash Boot Enable Enable PS booting PL from flash Disable PS booting PL from flash D10 Amber MVMRO Enab...

Page 12: ...nal MIO9 pin A24 It should be used to indicate that the board is performing self test or that the Programmable Logic PL section of the SoC is unconfigured 4 2 1 3 MVMRO XMC Write Prohibit This signal...

Page 13: ...s using DIP switch SW2 3 See Table 5 In independent mode the main chain with the Zynq PL CPLD and XRM interface is connected to J4 while the Zynq PS is connected to header J3 If the cascaded or main s...

Page 14: ...rence for the eight GTX lanes on Quads 111 and 112 Signal Target FPGA Input IO Standard P pin N pin PCIEREFCLK MGTREFCLK0_112 HSCL N8 N7 Table 8 PCIEREFCLK Connections 4 5 2 MGTCLK250M The fixed 250 0...

Page 15: ...us to the clocks generated by the Si5338B Signal Target FPGA Input IO Standard P pin N pin PS_CLK33M3 PS_CLK_500 LVCMOS18 A22 Table 12 PS_CLK33M3 Connections 4 5 6 USB_REFCLK24M The USB PHY and hub ar...

Page 16: ...used for the local bus interface between the Zynq PL and the BU 67301 Two phase matched copies of BU_HOST_CLCK_OUT should be generated by the Zynq PL on pins AD25 and AE26 BU_HOST_CLK_OUT_A on pin AD2...

Page 17: ...7 2 3 PS DDR3 Memory The PS has one bank of DDR3 memory constisting of 2 16 bit wide memory devices in parallel to provide a 32 bit datapath capable of running up to 533MHz DDR 1066 2Gb devices Micro...

Page 18: ...ADM XRC 7Z2 User Manual V1 2 24th Feb 2020 LED Colour Function 0 Green 1 Green 2 Amber Table 16 Ethernet Status LEDs Page 14 Functional Description ad ug 1273_v1_2 pdf...

Page 19: ...Interface Generator MIG Full details of the interface signaling standards are provided in the example design 4 8 2 1553 Bus Controller The PL is connected to a BU 67301B 1553 bus controller The pinout...

Page 20: ...d FPGA are being operated within the specified limits If the temperature is close to the limit a Warning Alarm interrupt is set If a limit is exceeded a Critical Alarm interrupt is set After the Criti...

Page 21: ...re or invalid firmware Red Green Standby Powered off Green Running and no alarms Flashing Green Red Attention alarm active Flashing Green Flashing Red together Attention critical alarm active Flashing...

Page 22: ...ADM XRC 7Z2 User Manual V1 2 24th Feb 2020 Page Intentionally left blank Page 18 Functional Description ad ug 1273_v1_2 pdf...

Page 23: ...VPWR 3 8 GND GND XMC_TDI GND GND 12V 9 VPWR 3 10 GND GND XMC_TDO GND GND GA0 11 PER0p0 PER0n0 MBIST PER0p1 PER0n1 VPWR 3 12 GND GND GA1 GND GND MPRESENT 13 PER0p2 PER0n2 3 3V AUX 2 PER0p3 PER0n3 VPWR...

Page 24: ...GND GND GPIO_SE8 GND GND GPIO_SE10 9 GPIO_2N GPIO_2P GPIO_SE9 GPIO_3N GPIO_3P GPIO_SE11 10 GND GND GPIO_SE4 GND GND GPIO_SE6 11 ETH1_TxN ETH1_TxP GPIO_SE5 ETH1_RxN ETH1_RxP GPIO_SE7 12 GND GND GPIO_SE...

Page 25: ...ADM XRC 7Z2 User Manual V1 2 24th Feb 2020 Page 21 Rear Connector Pinouts ad ug 1273_v1_2 pdf...

Page 26: ...ctions 24 02 20 1 2 Updated LED definitions with a diagram Address Suite L4A 160 Dundee Street Edinburgh EH11 1DQ UK Telephone 44 131 558 2600 Fax 44 131 558 2700 email sales alpha data com website ht...

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