ADM-XRC-7Z2 User Manual
V1.2 - 24th Feb 2020
4.7.4 Serial COM Ports
PL
P4
PHY
PS
PHY
COM1
COM2
Platform Mgr
COM0
I2C
RS-232
RS-232
COM1
COM2
Figure 5 : Serial COM Ports
4.7.5 USB Interfaces
PL
PHY
ULPI
4 port
Hub
P4
USB1
USB2
Micro
USB
0
0
0
ExtHostSel
Figure 6 : USB Interfaces
4.8 Zynq PL Block
4.8.1 PL DDR3 Memory
The PL has two banks of DDR3 memory, each constisting of a single 16-bit wide memory device, capable of
running up to 800MHz (DDR-1600). 2Gb devices (Micron MT41J64M16-187E) are fitted as standard to provide
256MB per bank.
The memory banks are arranged for compatibility with the Xilinx Memory Interface Generator (MIG). Full details
of the interface, signaling standards are provided in the example design.
4.8.2 1553 Bus Controller
The PL is connected to a BU-67301B 1553 bus controller. The pinout is available in the example design.
4.8.3 Rear GPIO Interface
There are 20 single ended GPIO and 16 differential pairs connected to the P6 connector. The pinout is available
in the example design.
4.9 System Monitoring
The 7Z2 has the ability to monitor temperature and voltage to maintain a check on the operation of the board.
The monitoring is implemented using an Atmel AVR microcontroller (uC).
The microcontroller continually measures all voltage rails and temperature sensors and transmits the results to
the FPGA, where they are stored in blockram.
Page 15
Functional Description
ad-ug-1273_v1_2.pdf
