ADM-XRC-7Z2 User Manual
V1.2 - 24th Feb 2020
Appendix A: Rear Connector Pinouts
Appendix A.1: Primary XMC Connector, P5
.
A
B
C
D
E
F
1: PET0p0
PET0n0
3.3V
PET0p1
PET0n1
VPWR
(3)
2: GND
GND
XMC_TRST#
GND
GND
MRSTI#
3: PET0p2
PET0n2
3.3V
PET0p3
PET0n3
VPWR
(3)
4: GND
GND
XMC_TCK
GND
GND
MRSTO#
5: PET0p4
PET0n4
3.3V
PET0p5
PET0n5
VPWR
(3)
6: GND
GND
XMC_TMS
GND
GND
+12V
7: PET0p6
PET0n6
3.3V
PET0p7
PET0n7
VPWR
(3)
8: GND
GND
XMC_TDI
GND
GND
-12V
9: -
-
-
-
-
VPWR
(3)
10: GND
GND
XMC_TDO
GND
GND
GA0
11: PER0p0
PER0n0
MBIST#
PER0p1
PER0n1
VPWR
(3)
12: GND
GND
GA1
GND
GND
MPRESENT#
13: PER0p2
PER0n2
3.3V AUX
(2)
PER0p3
PER0n3
VPWR
(3)
14: GND
GND
GA2
GND
GND
MSDA
15: PER0p4
PER0n4
-
PER0p5
PER0n5
VPWR
(3)
16: GND
GND
MVMRO
GND
GND
MSCL
17: PER0p6
PER0n6
-
PER0p7
PER0n7
-
18: GND
GND
-
GND
GND
-
19: 0
REFCLK-0
-
WAKE#
ROOT0#
-
Notes:
(1) PCIe Channel Lanes (7:0) are directly connected to the Target FPGA.
(2) 3.3V AUX is required.
(3) VPWR can be 5V or +12V.
Table 20 : XMC Connector P5
Page 19
Rear Connector Pinouts
ad-ug-1273_v1_2.pdf
