ADM-XRC-7Z2 User Manual
V1.2 - 24th Feb 2020
Note:
Clock Termination
The LVDS clocks do not have termination resistors on the circuit board. On-die terminations in the FPGA must
be enabled by setting the attribute "DIFF_TERM = TRUE". This can either be set in the source code when
instantiating the buffer, or in the User Constraints File (UCF).
4.5.1 PCIe Reference Clock (PCIEREFCLK)
The 100MHz PCI Express reference clock is provided by the carrier card through the Primary XMC connector,
P5, at pins A19 and B19. This is connected to the Zynq PL via 10nF AC coupling capacitors. On the Zynq PL, it
is connected to GTX Quad 112 to allow its use as reference for the eight GTX lanes on Quads 111 and 112.
Signal
Target FPGA Input
IO Standard
"P" pin
"N" pin
PCIEREFCLK
MGTREFCLK0_112
HSCL
N8
N7
Table 8 : PCIEREFCLK Connections
4.5.2 MGTCLK250M
The fixed 250.0MHz reference clock, MGTCLK250M, is a differential clock signal using LVDS. It is connected to
MGTREFCLK inputs on the Zynq PL at GTX Quad 111. (See Figure Figure MGT Links.)
Signal
Target FPGA Input
IO Standard
"P" pin
"N" pin
MGTCLK250M
MGTREFCLK0_111
LVDS_25
U8
U7
Table 9 : MGTCLK250M Connections
4.5.3 PROGCLK
The programmable clock, PROGCLK, is a differential clock signal using LVDS. It is connected to MGTREFCLK
inputs on the Zynq PL at GTX Quad 111. (See Figure Figure MGT Links.)
Signal
Target FPGA Input
IO Standard
"P" pin
"N" pin
PROGCLK
MGTREFCLK1_111
LVDS_25
W8
W7
Table 10 : PROGCLK Connections
Page 10
Functional Description
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