Alpha Data ADM-PA100, User Manual

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ADM-PA101 User Manual
3.2 Clocking
The ADM-PA101 provides flexible reference clock solutions for the many multi-gigabit transceiver quads, DDR4
banks, and PL fabric. Any programmable clock, from the Si5338 Clock Synthesizer, is reconfigurable from the
front panel Micro USB Interface by using Alpha Data’s avr2util utility. This allows the user to configure almost any
arbitrary clock frequency during application run time. The maximum clock frequency is 350MHz. Customers who
purchase RD-PA101 also have the option of embedding IP into their ACAP design that permits programmable
clock reconfiguration via PCIe or from within the ACAP.
There is one available Si5328 jitter attenuator. This can provide clean and synchronous clocks to the FMC+ quad
locations at many clock frequencies. These devices use volatile memory, so the ACAP design will need to
reconfigure the register map over I2C after any power cycle.
All clock names in the section below can be found in Complete Pinout Table .
SI5328_REFCLK_IN (MGTREFCLK1_200)
Si5328_0
(2.5V VCC)
Address: 1101000
CMODE = GND
I2C +
CNTRL
CLKOUT2
CLKOUT1
Crystal
114.285MHz
XA/XB
CLKIN1
CLKIN2
FPGA Bank 710
SI5328_1V5_SDA
SI5328_1V5_SCL
SI5328_0_RST_1V5_L
SI5328_1V5_INT_C1B
SI5328_1V5_C2B
SI5328_1V5_LOL
MGT_PROGCLK_0 (MGTREFCLK0_200)
PCIE_LCL_REFCLK 100MHz GTY_REFCLK0_104
PCIe
Edge
U36
(ASFLMPLV-
100.000MHZ-LR-T)
PCIE_REFCLK_0 100MHz std. GTY_REFCLK0_103
Buffer
NB6N11S PCIE_REFCLK_1 100MHz std. GTY_REFCLK0_105
FABRIC_CLK 300MHz Default (IO Bank 710)
25MHz
30ppm
Source Si5338
Clock
Synth
0
1
2
3
Buffer
CDCLVD1208
MEM_CLK_0 300MHz Default (IO Bank 701)
MEM_CLK_1 300MHz Default (IO Bank 704)
FIREFLY_CLK 350MHz Default (GTY_REFCLK0_206)
Buffer
NB6L11S
D
P
[0
-3
]
D
P
[4
-7
]
D
P
[8
-1
1]
D
P
[1
2-
15
]
D
P
[1
6-
19
]
D
P
[2
0-
23
]
FPGA quads connected to FMC+
SI5328_OUT_0 (MGTREFCLK1_201)
MGT_PROGCLK_1 (MGTREFCLK0_201)
GBTCLK2_M2C (MGTREFCLK1_202)
MGT_PROGCLK_2 (MGTREFCLK0_202)
GBTCLK3_M2C (MGTREFCLK1_203)
MGT_PROGCLK_3 (MGTREFCLK0_203)
SI5328_OUT_1 (MGTREFCLK1_204)
MGT_PROGCLK_4 (MGTREFCLK0_204)
GBTCLK6_M2C (MGTREFCLK1_205)
MGT_PROGCLK_5 (MGTREFCLK0_205)
MGT_PROGCLK_7 156.25MHz Default (GTY_REFCLK1_206)
FMC+
GBTCLK0_M2C
GBTCLK1_M2C
GBTCLK2_M2C
GBTCLK3_M2C
GBTCLK4_M2C
GBTCLK5_M2C
=> A build modification can connect this line
Figure 6 : Clock Topology
Page 9 Functional Description
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