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ID
Mode
Default
0x00
Off
0x01 reserved
0x02 Trigger
input
Input 1
0x03
Incremental decoder input
0x04 reserved
0x05
tbd (SPI external DCLK)
0x06..0x0F reserved
0x10..0x1F reserved
Trigger
If more than one input is being operated in
trigger mode
, these inputs are logically
linked by AND.
IO_OUTP_CTRL 1-3
The
Polarity
flag determines whether the output is low active (0) or high active (1). The
output mode
can be seen in the following table. The current status of the output can
be queried and set via the
PinState
flag.
Offset
Name
Field
Bit
Description
0xF1000320 IO_OUTP_CTRL1 Presence_Inq
[0]
Indicates presence of this
feature (read only)
---
[1..6]
-
Polarity
[7]
0: low active, 1: high
active
---
[8..10]
Output
mode [11..15] Mode
---
[16..30]
PinState
[31]
RD: Current state of pin
WR: New state of pin
0xF1000324 IO_OUTP_CTRL2 Same as IO_OUTP_CTRL1
0xF1000328 IO_OUTP_CTRL3 Same as IO_OUTP_CTRL1
Output mode
ID
Mode
Default
0x00 Off
0x01
Output state follows ‘PinState’ bit
0x02 Integration
enable Output 1
0x03
Incremental decoder compare
0x04
tbd (SPI internal DCLK)
0x05
tbd (SPI external DCLK)
0x06 FrameValid
0x07 Busy
Output 3
0x08 Follow
corresponding
input
(Inp1
→
Out1, Inp2
→
Out2, …)
Output 2
0x09..0x0F reserved
0x10..0x1F reserved
The “Polarity“ setting refers to the input side of the inverting optical coupler output,
“PinState 0” switches off the output transistor and produces high level over the
resistor.