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Allen-Bradley PLC-2/30, Programming And Operations Manual

The Allen-Bradley PLC-2/30 is a reliable programmable logic controller designed for industrial automation. For detailed instructions on programming and operations, download the free Programming And Operations Manual from manualshive.com. This comprehensive manual will guide users through set-up, troubleshooting, and maintenance of the PLC-2/30 system.

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Table of Contents

vi

12.5.1 Accessing the Data Monitor Mode

 

 1221

. . . . . . . . . . . . . . . . . . . 

12.5.2 Data Monitor Display

 

 1224

. . . . . . . . . . . . . . . . . . . . . . . . . . . . 

12.5.3 Cursor Controls

 

 1225

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

12.5.4 Data Monitoring Procedures

 

 1226

. . . . . . . . . . . . . . . . . . . . . . . 

12.5.5 Entering and Changing Data

 

 1227

. . . . . . . . . . . . . . . . . . . . . . . 

Shift Register Instructions

 

 131

. . . . . . . . . . . . . . . . . . . . . . . . . 

13.0 General

 

 131

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

13.1 Shift File Up

 

 132

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

13.1.1 Programming Shift File Up Instruction

 

 133

. . . . . . . . . . . . . . . . 

13.2 Shift File Down

 

 135

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

13.2.1 Programming Shift File Down Instruction

 

 135

. . . . . . . . . . . . . . 

13.3 FIFO Load and FIFO Unload

 

 136

. . . . . . . . . . . . . . . . . . . . . . . . 

13.3.1 Programming FIFO Load and FIFO Unload Instruction

 

 138

. . . . . 

Bit Shifts

 

 141

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

14.0 General

 

 141

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

14.1 Bit Shift Left

 

 141

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

14.1.1 Programming Bit Shift Left Instruction

 

 143

. . . . . . . . . . . . . . . . . 

14.2 Bit Shift Right

 

 145

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

14.2.1 Programming Bit Shift Right Instruction

 

 146

. . . . . . . . . . . . . . . 

14.3 Examine Off Shift Bit

 

 146

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

14.3.1 Programming Examine Off Shift Bit Instruction

 

 146

. . . . . . . . . . 

14.4 Examine On Shift Bit

 

 148

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

14.4.1 Programming Examine On Shift Bit Instruction

 

 148

. . . . . . . . . . 

14.5 Set Shift Bit

 

 149

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

14.5.1 Programming Set Shift Bit Instruction

 

 149

. . . . . . . . . . . . . . . . . 

14.6 Reset Shift Bit

 

 1410

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

14.6.1 Programming Reset Shift Bit Instruction

 

 1411

. . . . . . . . . . . . . . . 

Sequencer Instructions

 

 151

. . . . . . . . . . . . . . . . . . . . . . . . . . . 

15.0 General

 

 151

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

15.1 Sequencer Output Instruction

 

 153

. . . . . . . . . . . . . . . . . . . . . . . . 

15.1.1 Sequencer Output Analogy

 

 153

. . . . . . . . . . . . . . . . . . . . . . . . 

15.1.2 Operation of the Sequencer Output Instruction

 

 154

. . . . . . . . . . 

15.1.3 Masking Output Data

 

 155

. . . . . . . . . . . . . . . . . . . . . . . . . . . . 

15.1.4 Instruction Overview

 

 156

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

15.1.5 Programming the Sequencer Output Instruction

 

 156

. . . . . . . . . 

15.2 Sequencer Input Instruction

 

 1510

. . . . . . . . . . . . . . . . . . . . . . . . . 

15.2.1 Operation of the Sequencer Input Instruction

 

 1510

. . . . . . . . . . . 

15.2.2 Masking Input Data

 

 1510

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

15.2.3 Instruction Overview

 

 1510

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

15.2.4 Programming the Sequencer Input Instruction

 

 1511

. . . . . . . . . . . 

15.3 Sequencer Load Instruction

 

 1513

. . . . . . . . . . . . . . . . . . . . . . . . . 

Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com

Summary of Contents for PLC-2/30

Page 1: ...service in house repair center WE BUY USED EQUIPMENT Sell your excess underutilized and idle used equipment We also offer credit for buy backs and trade ins www artisantg com WeBuyEquipment REMOTE IN...

Page 2: ...PLC 2 30 Programmable Controller Programming and Operations Manual Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com...

Page 3: ...ability for actual use based upon the illustrative uses and applications No patent liability is assumed by Allen Bradley Company Inc with respect to use of information circuits equipment or software d...

Page 4: ...7 Industrial Terminal 2 7 2 8 Local System Structure 2 7 2 9 Remote System Structure 2 8 2 10 Local Remote System Structure 2 9 2 11 Hardware Addressing Modes 2 10 2 12 Auxiliary Power Supplies 2 10 2...

Page 5: ...3 4 Ending a Program 4 12 4 3 5 Programming Relay Type Instructions 4 13 4 4 Operating Instructions 4 14 4 4 1 Addressing 4 15 4 4 2 Help Directories 4 15 4 4 3 Searching 4 16 4 4 4 Editing 4 19 4 4 5...

Page 6: ...and Equ Instructions 6 4 6 2 2 Get Byte and Limit Test Instructions 6 7 6 2 3 Get Byte Put Instruction 6 8 6 3 Programming Data Manipulation Instructions 6 9 6 4 Arithmetic Instructions 6 11 6 4 1 Add...

Page 7: ...ridge Tape 8 7 8 4 3 Data Cartridge Verification 8 8 8 5 Ladder Diagram Dump 8 8 8 6 Total Memory Dump 8 8 Report Generation 9 1 9 0 General 9 1 9 1 Report Generation Commands 9 3 9 1 1 Message Contro...

Page 8: ...outine Instructions 11 3 11 1 2 Multiple Jumps to the Same Label 11 3 11 2 Label Instruction 11 6 11 3 Jump to Subroutine Instruction 11 7 11 3 1 Subroutine Area 11 10 11 3 2 Nested Subroutines 11 11...

Page 9: ...ramming Examine Off Shift Bit Instruction 14 6 14 4 Examine On Shift Bit 14 8 14 4 1 Programming Examine On Shift Bit Instruction 14 8 14 5 Set Shift Bit 14 9 14 5 1 Programming Set Shift Bit Instruct...

Page 10: ...17 0 General 17 1 17 1 File Search 17 1 17 2 File Diagnostics 17 4 Troubleshooting Aids 18 1 18 0 General 18 1 18 1 Bit Manipulation and Monitor 18 2 18 1 1 Bit Manipulation 18 2 18 1 2 Bit Monitor 1...

Page 11: ...exadecimal Numbering System B 6 Programming 01 Second Timers C 1 C 0 Introduction C 1 C 1 Time Base Selection C 1 C 2 Timer Accuracy C 2 C 3 10 Msec Timers Typical Applications C 4 C 4 Hardware Proces...

Page 12: ...is your entry into understanding the PLC 2 30 programmable controller To find what the topics are in the individual chapters Use the Table of Contents To get an overview of what that chapter presents...

Page 13: ...program operation the PLC 2 30 processor continuously monitors the status of input devices and based on user program instructions either energizes or de energizes output devices Because the memory is...

Page 14: ...ents From word address 4008 on the data table must be expanded in 128 word sections The I O image tables therefore can be configured in size from 1 to 7 I O racks Each rack added above one increments...

Page 15: ...KP2 1779 KP2R PLC 2 30 RS 232 1771 KG 1771 KGM 1771 KH Data Highway Non A B1 1771 KE 1771 KF 1770 KF2 Data Highway Fisher Provox 1771 KX1 Data Highway II Non A B1 1779 KFL 1779 KFM 1 Non Allen Bradley...

Page 16: ...ictable machine motion with possible damage to equipment and or injury to personnel Figure 1 1 ERR Message for Invalid Display of Processor Memory 113 14 1025 16 11314 02516 1770 T3 Display Actual con...

Page 17: ...Rack Fault 1 The condition that occurs because of a loss of communication between the processor and remote I O chassis 2 any diagnostic indicator that lights up to signal a rack fault Slot 1 The phys...

Page 18: ...ocessor in the test mode The user program is tested under simulated operating conditions without actually energizing any output devices All outputs are disabled in this switch position RUN This switch...

Page 19: ...s removed from a 1772 LH processor interface module data table values can be changed between word addresses 0108 and 3778 These values can be changed only when the processor is in the program mode or...

Page 20: ...is defined as illegal such as jump to a label that is not located closer to the end of program i e a jump backwards These errors become apparent only while the program is being executed so are termed...

Page 21: ...LT Illuminates when an error in the parity of data retrieved from memory is detected Changing the mode select switch to the PROG position or cycling line power may clear this fault condition Reloading...

Page 22: ...a power lock momentary or otherwise processors in the RUN or TEST mode attempt to read the local racks before the power supplies are ready This leads to a processor fault The fault may be identified b...

Page 23: ...perly set Refer to publications 1772 2 18 and 1771 6 5 37 respectively for information on their switch settings WARNING Switch No 1 of the 1771 I O chassis should be set to OFF for most applications T...

Page 24: ...on about the 1770 T3 Industrial Terminal refer to the Industrial Terminal System User s Manual publication no 1770 6 5 3 For detailed information about the 1784 T50 Industrial Terminal refer to the In...

Page 25: ...e system allows the processor and the I O chassis to be separated by up to 10 000 cable feet approx 3 048 meters Up to 7 remote I O racks may be assigned Proper transmission of data between the PLC 2...

Page 26: ...off NOTE For a full listing of the possible combinations of these indicators on off or blinking see the 1771 ASB User s manual publication no 1771 6 5 37 A local remote system has both nearby 3 6 cab...

Page 27: ...module can be addressed in either 2 slot 1 slot or 1 2 slot modes NOTE Processor to I O chassis communication requires the setting of I O chassis backplane switches See the 1771 ASB Remote I O Adapter...

Page 28: ...1 Series B I O chassis Full specifications are in publication no 1771 2 111 The 1771 P7 power supply provides 16 amperes to power one bulletin 1771 I O chassis This includes the adapter and the I O mo...

Page 29: ...0 1 1 0 0 0 1 0 0 1 0 1 1 0 1 1 1 0 0 1 17 16 15 14 13 12 11 10 07 06 05 04 03 02 01 00 1 0 0 1 0 1 0 1 1 0 0 0 1 0 0 0 0 1 1 1 1 0 0 0 1 0 0 1 0 0 0 0 17 16 15 14 13 12 11 10 07 06 05 04 03 02 01 00...

Page 30: ...ord address and are divided into three major areas Figure 3 2 Data table User program Main Program Subroutine Area Message Storage Area All input output status and user program instructions are stored...

Page 31: ...icate remote rack fault status in a remote I O system Do not put input modules in rack 2 I O groups 5 or 6 3 Report generation messages can be stored in memory locations not used by data table or user...

Page 32: ...modules cannot store information They contain interface circuits only Input output status information on off is actually stored in memory areas called I O image tables An image is defined as an exact...

Page 33: ...le therefore contains 16 word addresses or 256 bit addresses Using the industrial terminal the output image table can be reduced to 8 word addresses 128 bit addresses or increased from 16 word address...

Page 34: ...memory is cleared to off These bits are monitored by instructions in the user program Input image table bits are updated each scan cycle to correspond to the information supplied by input modules The...

Page 35: ...1258 and 1268 may be used to store remote I O fault bits If this is the case input modules must not be placed in these slots rack 2 I O groups 5 and 6 unexpected machine operation may result Artisan T...

Page 36: ...es in rack 2 I O group 7 2 These words are used to indicate remote rack fault status in a remote I O system Do not put input modules in rack 2 I O groups 5 or 6 Default Configured Data Table 128 Words...

Page 37: ...in an I O rack slot If it does the terminal address is the same as the bit address The correspondence between the two is illustrated in Figure 3 4 CAUTION Bit and or word storage is not possible in th...

Page 38: ...orage Bit 010 17 16 15 14 13 12 11 10 07 06 05 04 03 02 01 00 Input Image Word Assigned to an Input Module Terminal 010 Word Address Terminal Input Rack Address Module Group 32 I O 1771 A1B 64 I O 177...

Page 39: ...data table Determining the number of words needed and assigning addresses is a procedure that requires care and attention to detail The data table should be roughed out in advance but formally develo...

Page 40: ...ory layout display 1 Requires Series B Revision F or later keyboard Data Table Area Configuration The data table is factory configured for 128 words Figure 3 2 The data table size can be decreased to...

Page 41: ...equencer tables The calculation is made using the following formula ET T C IS 2 where ET number of equivalent timers and counters T number of timers C number of counters IS number of internal storage...

Page 42: ...ade available for user program instructions Reductions can be made in decrements as small as two words one timer counter If the memory locations are occupied the attempted reduction fails You can incr...

Page 43: ...racks accumulated address limits become 0608 to 0778 and the preset address limits become 1608 to 1778 when you increase the I O to 768 6 racks accumulated address limits are 0708 to 0778 and preset...

Page 44: ...as Examine On use one word of memory Others such as file instructions are more complex and can use two or more words of user program memory As the user program is entered from the industrial terminal...

Page 45: ...and all the bits in the upper byte of the message control words may be used for automatic report generation functions Since the user program examines these bits to determine report generation status a...

Page 46: ...logical address of a single 16 bit input or output image table word The remaining two digits represent a specific bit in that I O table word Figure 3 6 shows how the 5 digit address corresponds to an...

Page 47: ...rminology Input 1 or Output 0 Rack No 1 7 I O Group No 0 7 Terminal No 00 07 10 17 Word Address Bit Address Data Table Terminology Instruction Address Output 0 Rack No 1 Word Address Bit Address I O G...

Page 48: ...12 11 10 07 06 05 04 03 02 01 00 Bit Terminal Outout 0 Input 1 Rack Number Module Group 32 I O 64 I O 96 I O 128 I O Rack 1 I O Group 1 0 1 2 3 4 5 6 7 Word Address 010 Upper Byte Lower Byte Left Slot...

Page 49: ...r examines bit 113 12 for an On 1 condition If the bit is On 1 the Examine On instruction is logically true A true condition is displayed as an intensified instruction A path of logic continuity is es...

Page 50: ...0 OFF 012 Closed Input 0178 1138 1108 1778 06 12 113 Instruction Intensified When Enabled When the input device wired to terminal 113 12 opens the input module senses no voltage The Off condition is...

Page 51: ...s form can be used to map the addresses of group data table words and to concisely describe the function of each group The groups can include I O Image Tables Block Transfer Timer Counter File and Seq...

Page 52: ...storage bits The lower two digits of the 3 4 or 5 digit word address are prenumbered in the left hand column The bit numbers 00 17 complete the 5 6 or 7 digit bit address The starting word address can...

Page 53: ...e words can be numbered consecutively through the entire 64 words Or the right hand column can be numbered 1008 greater than the left hand column to conveniently track accumulated and preset values In...

Page 54: ...ge bits having the same I O group number The bit numbers are prenumbered 00 17 For example a portion of the data table bit assignment sheet is shown in Figure 3 11 It illustrates logging the input dev...

Page 55: ...tten in the left hand blank column The from to addresses at the bottom of the sheet are the starting and ending file addresses for each column of the sequencer tables For example Figure 3 12 shows a c...

Page 56: ...he controller The 5 digit bit address directly corresponds to the location of each I O device with respect to the rack number I O group and terminal number Because the bit address is hardware related...

Page 57: ...C address pair as its data address The first available location must be reserved for block transfer Chapter 10 Table 3 B Timer Counter Address for 1772 LP3 I O Racks First Timer Counter Word Address 1...

Page 58: ...iately below the last timer counter preset address Files can include their own unique addresses as well as duplicate preassigned addresses Therefore files should be carefully entered on data table doc...

Page 59: ...3 3 31 ALLEN BRADLEY Connection Diagram Addressing BULLETIN 1771 I O Chassis PROJECT NAME PAGE DATE DESIGNER OF 8 point Modules Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURC...

Page 60: ...3 3 32 Bulletin 1771 I O Chassis CONNECTION DIAGRAM ADDRESSING WORKSHEET 16 point Modules PROJECT NAME PAGE DATE DESIGNER OF Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE...

Page 61: ...S WORD ADDRESS REF 000 040 100 140 200 240 300 340 400 440 500 540 600 640 700 740 037 077 137 177 237 277 337 377 437 477 537 577 637 677 737 777 ADDRESS TO 000 040 100 140 200 240 300 340 400 440 50...

Page 62: ...40 41 42 43 44 45 46 47 50 51 52 53 54 55 56 57 60 61 62 63 64 65 66 67 70 71 72 73 74 75 76 77 DESCRIPTION BIT NUMBER 17 10 07 00 STARTING WORD ADDRESS 00 01 02 03 04 05 06 07 10 11 12 13 14 15 16 17...

Page 63: ...E PROCESSOR DATA TABLE SIZE DESIGNER 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 WORD ADDR DESCRIPTION WORD ADDR DESCRIPTION 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3...

Page 64: ...4 5 6 7 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 WORD BIT DESCRIPTION WORD BIT DESCRIPTION Commen...

Page 65: ...UENCER TABLE BIT ASSIGNMENTS PAGE OF SEQUENCER COUNTER ADDR FILE to SEQ LENGTH WORD ADDR MASK ADDR MASK STEP 17 10 07 00 FROM ADDR TO ADDR 17 10 07 00 17 10 07 00 17 10 07 00 WORD 1 WORD 2 WORD 3 WORD...

Page 66: ...ble words The words remaining in memory can be determined by subtracting that number from the total memory available The text of this manual uses the following notational conventions to aid you when e...

Page 67: ...dder diagram rung in Figure 4 2 shows the two input devices and the output device that are assigned bit addresses in the data table The bit addresses correspond to the location of the I O devices wire...

Page 68: ...agram rung Figure 4 3 As condition instructions their on or off states determine the true or false condition of the rung Any bit in the data table excluding the processor work areas can be addressed b...

Page 69: ...4 Figure 4 4 Examine On Instruction 04 13 112 012 Examine Off Instruction The Examine Off instruction is the logical opposite of the Examine On instruction It tells the processor to check the status o...

Page 70: ...ut Latch L Output Unlatch U These instructions are used to set memory bits on or off in any area of the data table excluding the processor work areas and the input image table Output Energize Instruct...

Page 71: ...tion 15 035 Output Latch and Unlatch Instructions There are two output instructions that are termed retentive These instructions are Output Latch L Output Unlatch U These instructions are usually used...

Page 72: ...been latched on Figure 4 8 When the rung conditions for the Output Unlatch instruction go true the addressed memory bit is reset to zero off Figure 4 9 The output unlatch is also retentive This means...

Page 73: ...OG position the addressed memory bit and output device if latched on will immediately be energized regardless of rung conditions WARNING Do not preset a bit on controlled by Latch Unlatch instructions...

Page 74: ...each parallel logic branch of a rung The Branch Start is programmed immediately before the first instruction of each parallel logic path Branch End This instruction completes a set of parallel branch...

Page 75: ...N or OFF may not be the logically expected state of the rung This condition exists until the BRANCH END instruction is installed and the rung is completed Solution To avoid the above condition adhere...

Page 76: ...want to change the logic and insert the BRANCH START 3 Insert the desired parallel logic see Figure 4 14 4 Insert the BRANCH END Figure 4 14 Example New Rung With Branch Instruction 00 110 03 110 01 1...

Page 77: ...n The END statement also appears before program steps are entered When a user supplied teletypewriter or keyboard printer is used the END statement is printed on the hardcopy printout At the right of...

Page 78: ...t address 010 00 is displayed with a reverse video character cursor positioned at the first digit This cursor indicates where information is needed and moves to the next digits as information is enter...

Page 79: ...ATCH instruction is initially OFF when entered as indicated below the instruction It can be preset ON by pressing a 1 after entering the bit address An ON will then be indicated below the instruction...

Page 80: ...essed at any time provided the last digit has not been entered If the last digit was entered the instruction must be removed and the entire address must be re entered Word addresses unlike bit address...

Page 81: ...Shift Register Any SHIFT REG HELP Provides a list of all instructions that use the SHIFT REG key All Directories Any CANCEL COMMAND To terminate The industrial terminal can be used to search the user...

Page 82: ...Address keys Locates this address in the program excluding instructions and addresses in file Press SEARCH to locate the next occurrence of this address 1 Single rung display Any SEARCH DISPLAY Displ...

Page 83: ...n to the left To bring it back on the screen press the key The output instruction can be accessed from anywhere in the rung by pressing SEARCH in any mode Single Rung Display Upon power up a multiple...

Page 84: ...l keyboard can be used to change the processor mode when the keyswitch is in the RUN PROGRAM position The following key sequences can be used SEARCH 590 for run program mode SEARCH 591 for remote test...

Page 85: ...a word or block instruction ON LINE Run Program SEARCH 5 1 Data INSERT CANCEL COMMAND Position the cursor on the word or block instruction whose data is to be changed Press the key sequence Cursor ke...

Page 86: ...ed The input image table bits will be rewritten during the next I O scan If the wrong instruction is pressed an INSTRUCTIONS DO NOT MATCH message will be displayed Inserting a Rung A rung can be inser...

Page 87: ...ugh not displayed will position itself on the first data digit Enter that digit to display the cursor Then cursor back to the address digits using the key and change the address as needed Use a leadin...

Page 88: ...rechecked for accuracy All possible sequences of machine operation resulting from the change should be assessed in advance Be absolutely certain that the change must be done on line and that the chan...

Page 89: ...17 and BCD value bits 00 13 During program execution these bits are constantly changing to reflect current states and values of program instructions Therefore when programming on line a decision must...

Page 90: ...address or when it is desirable to enter new data and clear the status bits of an already used address The DATA INIT key should be pressed after the instruction key s and before the address is entered...

Page 91: ...the RECORD key is pressed CAUTION When the RECORD key is pressed the instruction is entered into memory immediately If the rung logic is true the output instruction will be enabled The procedure for...

Page 92: ...ON When the RECORD key is pressed the instruction will be removed immediately If the removal of the instruction causes the rung logic to become true the output will be enabled immediately NOTE Bit val...

Page 93: ...latch and unlatch instructions are cleared to zero All other word and bit addresses are not cleared when the rung is removed Change an Instruction or Instruction Address An instruction can be replaced...

Page 94: ...of the following procedures Step 1 Using the and cursor control keys cursor back the digit containing the error and correct it Step 2 Press the CANCEL COMMAND key It restores the ladder diagram displa...

Page 95: ...key sequence SHIFT SEARCH Step 2 Place the cursor at the end of the rung Step 3 Complete the rung by changing the blank output to the desired output instruction using the procedure Changing an Instru...

Page 96: ...le User Program and Messages 1 When Memory Write Protect is active memory cannot be cleared except for Data Table addresses 010 377 Data Table Clear Part of all of the data table can be cleared by pre...

Page 97: ...tions exist because of the industrial terminal screen size Only one output instruction can be programmed in a rung Program only one rung to energize an output device to simplify troubleshooting and ma...

Page 98: ...ondition instructions can be used with a Sequencer Input instruction if the output is a block instruction Up to 2 branches containing condition instructions can be used in parallel with a Sequencer In...

Page 99: ...the output is not a block instruction Up to 3 Examine On or Off Shift Bit instructions can be used in series if the output is a block instruction Up to 4 branches containing condition instructions can...

Page 100: ...Value Stored in the preset value area of the data table always 1008 words greater than its corresponding AC value This value is entered into memory by the user The preset value is the number of timed...

Page 101: ...ls and stores this count in its accumulated value word When timing is complete when AC PR bit 15 is either set on or off depending on the type of timer instruction For all timers bit 17 is set on when...

Page 102: ...se intervals As long as conditions remain true it increments its accumulated value word for each counted interval When the accumulated value equals the programmed preset value the timer stops incremen...

Page 103: ...tatus Bits are Reset When Input Switch is Opened Input Switch 113 02 Enable Bit 003 17 Preset Value Accumulated Value Timed Bit 033 15 Output Lamp 011 04 Rung 1 TON Instruction Preset for 9 Sec Delay...

Page 104: ...go false The enable bit bit 17 goes false when the timer begins rung 1 As long as its rung conditions remain false the TOF continues to time until the accumulated value equals the preset value When t...

Page 105: ...Accumulated Value Timed Bit 047 15 Output Lamp 011 04 Rung 1 TOF Instruction Preset for 9 Sec Delay Rung 2 Timer Turns Off Bit 011 04 When Timed Out 05 TOF 1 0 113 047 15 04 047 011 PR 009 AC 009 Inp...

Page 106: ...le Bit 052 17 Preset Value ACC Value Retained When Rung Condition Goes False Accumulated Value Timed Bit 052 15 Output Lamp 011 04 Rung 1 Retentive Timer Preset for 9 Sec Delay Rung 2 Timer Turns On B...

Page 107: ...t of the retentive timer Figure 5 5 rung 3 to zero This instruction is given the same word address as its corresponding RTO instruction Figure 5 5 When rung conditions go true the RTR instruction rese...

Page 108: ...cant Digit Accumulated Value in BCD Form Overflow Underflow Bit Set to 1 When CTU Overflows 999 or CTD Underflows 000 Down Counter Enable Bit Set to 1 When AC PR Up Counter Enable Bit The Up Counter C...

Page 109: ...5 6 7 8 9 10 11 Overflow Bit Comes On at 1000th Event The Counter Does Not Reset Event to be Counted 111 11 AC PR 997 998 999 1 2 0 Accumulated Value ON OFF Enable Bit 053 17 ON OFF Count Complete Bi...

Page 110: ...re 5 8 Figure 5 8 Counter with Reset Diagram for Preset 9 and Programming ON OFF 1 2 4 5 6 7 8 9 10 11 Event to be Counted 111 11 AC PR 12 1 2 Accumulated Value ON OFF Enable Bit 053 17 ON OFF Count C...

Page 111: ...position Rung conditions go false Power outage occurs provided memory backup power is maintained for CMOS RAM memory Each time the CTD rung goes true bit 16 the enabled bit is set on When the Accumul...

Page 112: ...y a value other than 000 For this reason a Get Put transfer Section 6 1 rather than a CTR instruction is usually used to load a value in the CTD Accumulated Value word Get Put instructions are discuss...

Page 113: ...Counter 051 Then Overflow Bit Resets Counter 050 06 110 Timer and Counter instructions are entered into memory with the processor in the program mode Timer instructions are programmed by entering a w...

Page 114: ...ically enters a 4 or 5 digit default word address depending on the data table size When a 4 or 5 digit word address is displayed and a 3 or 4 digit word address is required the programmer must enter l...

Page 115: ...ed Value at a rate specified by the time base When the rung is FALSE the timer resets the Accumulated Value to 000 See Note TOF TIMER OFF DELAY XXX TOF TB PR YYY AC ZZZ When the rung is FALSE the time...

Page 116: ...the CTU Accumulated Value and status bits are reset to 000 See Note CTD DOWN COUNTER XXX CTD PR YYY AC ZZZ Each time the rung goes TRUE the Accumulated Value is decreased one count The Accumulated Val...

Page 117: ...rst 1000 scans When the counter overflows the timer stops Rung 4 gets the value of the timer after 1000 scans and displays it in milliseconds as the result of the divide instruction Rung 5 and 6 reset...

Page 118: ...x Store 2 xxx To enable the programmer to estimate the scan time a proposed program may require the average execution times required for PLC 2 30 instructions are presented in Tables 5 D through 5 G T...

Page 119: ...File down instruction having a file 18 words long has an execution time see Table 5 E T 107 7 4 18 107 133 2 240 microseconds File Search and File Diagnostic instructions must be increased by a facto...

Page 120: ...t1 Put1 G PUT 5 8 6 6 Les1 Equ1 7 4 6 6 Get Byte1 Limit Test1 B L 4 5 4 5 Add1 Subtract1 Multiply1 Divide1 BCD BIN1 BIN BCD1 x CONVERT 0 CONVERT 1 8 6 8 6 51 0 91 0 59 6 37 2 Branch Start1 Branch End1...

Page 121: ...depends on a length of files and b number of words step Section 5 6 2 2 Execution Time is increased by 4 6 x the number of words searched before a match is found Section 5 6 2 3 Execution Time is incr...

Page 122: ...s Table 5 F Average Execution Times For File to File Move and File Complement Instructions Time Microseconds Rate Words per Scan Dist Complete Mode Complete Mode 5 10 15 25 50 100 256 512 119 153 187...

Page 123: ...ey require 6 microseconds The first scan the rung is false after the done bit is set requires 17 6 microseconds to reset flags and counters Table 5 G Average Execution Times In Microseconds For FILE T...

Page 124: ...of 3 digit binary coded decimal numbers The Les and Equ instructions compare data such as 3 digit numeric values in BCD format using the lower 12 bits of a data table word Figure 6 1 This 3 digit valu...

Page 125: ...te 2 1 0 0 1 1 0 0 1 1 1 1 0 1 1 1 1 Bits 00 07 Contain Octal Value of Lower Byte Bits 10 17 Contain Octal Value of Upper Byte 3 18 3 5 78 21 20 21 20 22 21 20 22 21 20 21 20 22 21 20 22 There are thr...

Page 126: ...transfer will occur Data transfer occurs only when the rung is true The Get instruction can be programmed either at the beginning of a rung or with one or more condition instructions preceding it Cond...

Page 127: ...n instructions are LESS THAN EQUAL TO GET BYTE B LIMIT TEST L Data comparison operations differ from data transfer operations in that data table values are not transferred Instead the values at differ...

Page 128: ...han comparison is made with the Get Les pair of instructions The BCD value of the Get instruction is the changing value It is compared to the BCD value of the Les instruction the reference value Figur...

Page 129: ...re 6 7 Equal To Comparison 03 02 120 010 G YYY 030 100 035 Reference Value When YYY 100 GET EQU comparison is true and 010 02 is energized Less Than or Equal To This comparison is made using the Get L...

Page 130: ...TE Only one Get instruction is required for this parallel comparison The Les and Equ instructions are programmed on parallel branches Figure 6 9 Greater Than or Equal To Comparison 05 04 120 010 G 440...

Page 131: ...tal value stored in that byte is then compared to the upper and lower octal values of the Limit Test instruction If the Get Byte value is equal to or between the Limit Test values the comparison is tr...

Page 132: ...keyboard with the processor in the program mode When entered they are displayed as intensified and blinking and will continue to blink until all information is entered The default word address 010 can...

Page 133: ...ess See Note LESS THAN XXX YYY The LESS THAN instruction should be preceded by a GET instruction 3 digit BCD values at the GET and LESS THAN word addresses are compared If the logic is TRUE the rung i...

Page 134: ...uction Other condition instructions if used should be programmed before the Get instructions The arithmetic instructions are programmed in the output position of the ladder diagram rung They are assig...

Page 135: ...rmation on Binary and BCD number systems The Add instruction tells the processor to add the two values stored in the Get words The sum is then stored at the Add instruction word address When the sum e...

Page 136: ...tract word bit 16 is set on In the run test or run prog mode the negative sign will appear on the industrial terminal screen Figure 6 14 Subtract Instruction 14 009 111 042 G 100 130 G 109 041 Must be...

Page 137: ...t Get instruction value by the second Get instruction value The result is stored in two data table words addressed by the Divide instruction Figure 6 16 Usually two consecutive data table word locatio...

Page 138: ...red Refer to Table 6 B for a summary of these instructions A 3 4 or 5 digit default word address 010 0010 or 00010 will be displayed above the instruction provided the data table is expanded according...

Page 139: ...ULTIPLY instruction is an output instruction It is always preceded by two GET instructions which store the values to be multiplied See Note Two word addresses are required to store the 6 digit product...

Page 140: ...alues are governed by the I O rack configura tion BCD ADDR Address where the first three digits of the BCD number are stored The second three digit address is where the three least significant BCD dig...

Page 141: ...inary number The upper 4 bits of the binary data will be transferred to the lower 4 bits of the lower BCD address If the binary data changes while the rung is true the BCD result will also change If t...

Page 142: ...initially displayed 3 4 or 5 will depend on the size of the data table Initially displayed default values are governed by the I O rack configura tion BINARY ADDR Stores the binary number BINARY DATA T...

Page 143: ...r 6 6 20 Figure 6 20 Binary to BCD Conversion Example Rung BINARY TO BCD BINARY ADDR 025 DATA 111111111111 BCD ADDR 201 202 DATA 004095 025 OV 14 Artisan Technology Group Quality Instrumentation Guara...

Page 144: ...system should not be operated without a hard wired master control relay and emergency stop switches to provide emergency I O power shut down Emergency stop switches can be monitored but should not be...

Page 145: ...n in their last state When MCR zone is false nonretentive outputs are de energized The MCR and ZCL instructions control the zoned outputs differently MCR When false all nonretentive outputs within the...

Page 146: ...speeds up the response of output devices to the program and the update of input data for program use The immediate I O instructions are usually used where I O modules interface with I O devices that o...

Page 147: ...tructions are scanned and executed in the order in which they were entered except where jumps and subroutines are used The scan sequence when jumps and subroutines are employed is described in those s...

Page 148: ...iate Input instruction only when necessary This depends on both the response time of the specific input devices and modules and on the position of the rungs examining these inputs in the program It is...

Page 149: ...ate Output instruction only when necessary This depends on the response time of output modules and devices and on the position of the rungs addressing the module group The Immediate Output instruction...

Page 150: ...m Scan Module Group Output Immediate Output Instruction Interrupts Program Scan Word 014 I O Scan Program Scan Control Bits of Word 014 Here in Program Writes all 16 Bits from one Output Image Table W...

Page 151: ...Two MCR instructions are required to control a group of outputs The first MCR instruction is programmed with input conditions to begin the zone The second MCR instruction is programmed unconditionally...

Page 152: ...5 Unlike local I O racks each remote I O rack can have up to 128 I O points using one of the following arrangements One 128 I O chassis Two 64 I O chassis One 64 I O chassis and two 32 I O chassis Fou...

Page 153: ...0 1 2 3 Module Groups 4 5 6 7 Module Groups 0 1 Module Groups 2 3 Module Groups 4 5 Module Groups 6 7 Module Groups Remote I O Scanner Distribution Panel Rack 4 Remote Rack 3 Remote Rack 2 Remote Rac...

Page 154: ...rack Table 7 B For example bits 125 078 125 048 correspond to rack 1 and bits 125 038 125 008 correspond to rack 2 Although bits 126 138 126 108 are not used as fault status bits they cannot be used...

Page 155: ...ts 125 138 and 125 128 will be set on By selecting either dependent or independent fault zone programming the user can disable certain parts of the program or the entire program when a fault occurs in...

Page 156: ...tus bits as Examine Off conditions for the MCR or ZCL zones Figures 7 7 and 7 8 When a fault occurs in a remote I O chassis the corresponding fault status bit is set on The MCR or ZCL zone conditioned...

Page 157: ...25 Programming for Rack Groups 2 and 3 Independent programming for I O configuration in Figure 7 5 When a fault status bit is set on the MCR or ZCL zone is false and controls all outputs in the zone M...

Page 158: ...125 15 125 14 125 13 125 11 125 The time required to perform scans of I O differs depending upon whether the I O racks are local or remote The scan time for local systems is 0 5 ms per rack The scan t...

Page 159: ...ds and if it times out a processor fault occurs and the system shuts down If the time for complete scan exceeds 115 milliseconds the watchdog timer will time out and the processor will fault The watch...

Page 160: ...s 100 microseconds per scan When FALSE execution time is 17 6 microseconds Table 7 D The Following Instructions Reset the Watchdog Timer File To File Move Word To File Move File To Word Move File To F...

Page 161: ...other than the Data Cassette Recorder Cat No 1770 SA or Digital Cartridge Recorder Cat No 1770 SB is used The communication rate is the number of bits per second baud sent to from channel C The baud f...

Page 162: ...data table bit excluding the processor work areas can be accessed by the contact histogram command The status of the bit on or off and the length of time the bit remained on or off in hours minutes a...

Page 163: ...connecting peripheral device to Channel C and selecting proper baud rate To terminate After pressing DISPLAY the data of the histogram will be displayed on every other line with 5 frames of data per...

Page 164: ...ng RECORD 0 on the PLC 2 Family overlay and by pressing RECORD ON TAPE on the cassette recorder As memory is being recorded the industrial terminal will count and display the number of data table word...

Page 165: ...ber of program errors and whether the data table was verified will be displayed The automatic verification command will self terminate when complete If program errors exist they can be displayed and l...

Page 166: ...ry The data cartridge recorder can be operated from the industrial terminal keyboard It can also be operated in the same manner as a 1770 SA digital cassette recorder using both the recorder control p...

Page 167: ...ta table of the taped program Set the data table size as described in Section 3 2 1 Data Table Configuration If the size of the data table on tape is not immediately available and the processor is con...

Page 168: ...overlay The printout will begin from the current rung allowing all or part of the program to be printed When the printout is complete this command is automatically terminated This command can be termi...

Page 169: ...minated The total memory dump command can be terminated prior to completion by pressing ESC on the peripheral printer or CANCEL COMMAND on the PLC 2 family overlay Figure 8 2 Data Table Printout in He...

Page 170: ...y 2 or 3 rungs of programming are required to display a message by program logic Intelligent printer interface the RG module can monitor a busy ready signal from the printer Selectable communication r...

Page 171: ...ation rate to 19 200 bits Selectable number of data bits you can choose either seven or eight data bits per character Messages can be entered into memory from either the T3 industrial terminal or a pe...

Page 172: ...s entered by pressing RECORD DISPLAY on the PLC 2 Family keytop overlay There are 6 report generation commands used to enter control words and to store print report and delete messages and to display...

Page 173: ...1 CANCEL COMMAND can only be used if the function was entered by a command from a peripheral device 2 Requires Series B Revision F or later keyboard Bits from eight consecutive user selected words co...

Page 174: ...mpt MESSAGE ALREADY EXISTS While entering a message each key pressed except the SHIFT CTRL ESC or RUB OUT keys generates a code that is stored in one byte of memory This includes ASCII and graphic cha...

Page 175: ...s desired to report the output condition or or off of a device SR6 during each cycle of machine operation Delimiters would be used to denote the output address 013 05 and the cycle counter accumulativ...

Page 176: ...inted ESC or CANCEL COMMAND can be used to return to ladder diagram display Accessible in any mode the message index command prints a list of the message numbers used and the amount of memory in words...

Page 177: ...es 3 words of memory storing CRTL P in one byte and each remaining character in one byte each If the cursor had been at column 0 line 0 and normal space and line feed commands were used it would have...

Page 178: ...inuously until REPT LOCK is pressed again SHIFT Allows the next key pressed to be a shift character SHIFT LOCK Allows all subsequent keys pressed to be shift characters until SHIFT or SHIFT LOCK is pr...

Page 179: ...capability CTRL P 5 P Turns Channel C Outputs ON CTRL P 4 P Turns Channel C Outputs OFF CTRL I Horizontal tab that moves the cursor to the next preset 8th position CTRL K Clears the screen from curso...

Page 180: ...DATA LINK ESCAPE DEVICE CONTROL 1 DEVICE CONTROL 2 DEVICE CONTROL 3 DEVICE CONTROL 4 NEGATIVE ACKNOWLEDGE SYNCHRONOUS IDLE END OF TRANSMISSION BLOCK CANCEL END OF MEDIUM SUBSTITUTE ESCAPE FILE SEPARAT...

Page 181: ...ure 9 3 Figure 9 3 Parity Switch Location Halftone Once automatic report generation is activated the message request bits are scanned by the industrial terminal for zero to one transition Each time on...

Page 182: ...it 12 of the third message control word would request message 312 on a false to true transition Figure 9 4 Figure 9 4 Bit Address Message Number Relationship Control Word Number Message Numbers Contro...

Page 183: ...re placed in corresponding slots Hazardous or unexpected machine operation could result Damage to equipment and or personal injury could result Using latch and unlatch instructions automatic report ge...

Page 184: ...t Generation Chapter 9 9 15 Figure 9 6 Example Program to Request a Message L U Event Event Done Request Request Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg...

Page 185: ...tional module can use both the read and write operations During a read operation data is read into the processor s memory from the module During a write operation data is written to the output module...

Page 186: ...ite bit that controls the direction of transfer are set by a bit pattern in the output image table byte 2 I O scan The processor requests a transfer by sending the output image table byte data to the...

Page 187: ...r counter data and addresses is shown in Table 10 A After locating the file address in the timer counter area of the data table the processor then duplicates and transfers the file data consecutively...

Page 188: ...ile 1008 above the data address ENABLE BIT EN Automatically entered from the module address Set on when rung containing the instruction is true DONE BIT DN Automatically entered from the module addres...

Page 189: ...le to decide the number of words to be transferred See the data sheet or user s manual pertaining to the module for additional information The block length heading of the instruction will accept any v...

Page 190: ...ey sequence BLOCK XFER 0 for write and BLOCK XFER 1 for read Misuse and or inadvertent changes of instruction data can cause run time errors when The module address is given a non existent I O rack nu...

Page 191: ...d Last File Word Input image table byte contains done bit Storage location of file address contains file address in BCD R Bit 17 Read BLOCK XFER READ DATA ADDR 030 MODULE ADDR 121 BLOCK LENGTH 08 FILE...

Page 192: ...ck transfer read instructions would be used one for each desired transfer length starting at the same first word The read instructions would have the same module address data address and file address...

Page 193: ...al for any information unique to that module The programming example shown in Figure 10 5 illustrates how multiple reads of different block lengths from one module can be programmed When any one of th...

Page 194: ...RANSFER READ DATA ADDR 052 MODULE ADDR 141 BLOCK LENGTH 03 FILE 160 167 014 EN 17 114 DN 17 014 17 2 3 1 2 3 1 2 3 Inputs Inputs Inputs Input 1 Input 2 Input 3 NOTES 1 The same discussion applies when...

Page 195: ...chance be in the same configuration as the rack group and slot numbers found in block transfer data addresses The boundary word data bits can be set to zero manually using bit manipulation SEARCH 53 o...

Page 196: ...data in the buffer is valid it is immediately transferred to another file in the data table where it can be used If invalid it is not transferred but written over in the next transfer Another techniq...

Page 197: ...transfer B Diagnostic Bit is TRUE for each word to be moved in rungs 5 7 valid data 00 02 010 010 U 00 010 11 EN 07 111 014 BLOCK TRANSFER READ DATA ADDR 030 MODULE ADDR 140 BLOCK LENGTH 03 FILE 050 0...

Page 198: ...1 and 052 will be transferred to words 151 and 152 if the diagnostic bit is on Bidirectional block transfer is the sequential performance of both operations The order of operation is generally determi...

Page 199: ...ransfer Chapter 10 10 15 The data table locations and block instructions for this example are shown in Figure 10 8 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisan...

Page 200: ...OCK LENGTH 05 FILE 060 064 DN 06 113 Data Table W R 1 W 1 3 0 041 1 Block Transfer Read File 0 6 0 141 010 Output Image Table Low Byte Data Addresses 5 words of data table are to be written to the bid...

Page 201: ...ses are required one to receive data transferred from the module the other containing data to be transferred to the module In this example they are 060 and 070 The consecutive storage locations contai...

Page 202: ...il the Done bit is set Unequal Block Lengths Consult the user s manual for the block transfer module of interest for programming guidelines when setting the block lengths to unequal values WARNING Whe...

Page 203: ...subroutine can be called upon repeatedly from selected points in the main program Subroutines can be used to conserve memory in applications where repetitive programming is required or when sections...

Page 204: ...program execution jumps to label 07 13 117 Reprogram rungs that require updates when jump is active rung 3 is reprogrammed Jumped sections of programs are not scanned A Jump instruction can be progra...

Page 205: ...uts are not updated and outputs remain in their last state Timers and counters cease to function Critical rungs should be reprogrammed outside the jumped section of the program The Jump Subroutine ins...

Page 206: ...XX JMP When rung is TRUE processor jumps forward to the referenced LABEL in Main Program XX two digit octal identification number Same as LBL with which it is used RET JSR JUMP TO SUBROUTINE XX JSR Wh...

Page 207: ...11 4 Multiple JUMPS to LABEL in Subroutine Area Subroutine Area 1st Subroutine 2nd Subroutine To Main Program From JSR 03 From JSR 04 JMP 02 LBL 03 LBL 04 RET JMP 02 LBL 02 RET Artisan Technology Grou...

Page 208: ...e assigned octal identification numbers from 00 77 The label identification number must be the same as that of the Jump and or Jump to Subroutine instruction with which it is used A label instruction...

Page 209: ...injury could result NOTE Care should be taken not to misuse the Jump instructions and subroutine programming Misuse generally results in a run time error which causes the processor to fault Misuse of...

Page 210: ...put instruction Must always jump from main program into subroutine area or from one subroutine to another Can jump 1 or more times to the label with the same identification number Uses 1 word of memor...

Page 211: ...ction after subroutine jump 046 12 NOTE Do not misuse the Jump to Subroutine instruction Misuse generally results in a run time error which causes the processor to fault Misuse will cause the followin...

Page 212: ...the main program It cannot be inserted between rungs It requires one memory word can be programmed only once and cannot be removed except by clearing the entire subroutine area or the entire memory Up...

Page 213: ...til eight levels of calls are involved Figure 11 10 a shows three levels of nested subroutines The main program calls Level 1 at label 01 a Level 1 in turn calls Level 2 at label 02 b Note that Level...

Page 214: ...n program are causes of run time error If an output instruction in the subroutine area is left on after the processor has completed the program scan the output will remain on regardless of its rung co...

Page 215: ...el 1 Subroutine Level 2 Subroutine Level 3 JSR RET JSR RET RET 02 03 JSR 01 Main Program LBL 01 LBL 02 LBL 03 a b c d e f Subroutine Area A LBL SCT 01 051 15 JSR 051 01 PR 999 AC 000 JSR 01 Main Progr...

Page 216: ...truction does not have a user assigned identification number because it may be paired by the processor with any one of several JSR instructions as the result of multiple jumps to the subroutine area T...

Page 217: ...es the number of words in the file file length with its preset value It points to a particular word in the file position with its accumulated value The counter address is also referred to as the instr...

Page 218: ...dvertently programmed to overlap or be totally contained within another Care should be taken in assigning file areas to avoid unintentionally altering the contents of one file by the operation of anot...

Page 219: ...en the rung condition is true and or when the instruction is operating DONE BIT DN Automatically entered from the counter address Set high when the operation is complete and remains high as long as th...

Page 220: ...As long as the rung is true the operation will take place each scan If the counter accumulated value position changes while the rung is true the data at the new position will be operated upon An examp...

Page 221: ...ed in Table 12 A Table 12 A Modes of Instruction Operation Mode of Operation R Rate Per Scan Number of Words Operated Upon COMPLETE R File Length Entire file per scan DISTRIBUTED COMPLETE 0 R File Len...

Page 222: ...alse to true transition of the rung condition The rung would have to go false and then true after the operation is complete in order to repeat the instruction If the rung remained true on subsequent s...

Page 223: ...gram scans This is to avoid overextending the scan time of any one program scan This scan can be done by selecting the distributed complete mode Any rate per scan R can be chosen where 0 R 4 file leng...

Page 224: ...e results of a File instruction operating in the distributed complete mode until the done bit is set At completion the rung containing the instruction could either be true or false If the rung is true...

Page 225: ...than 1 Scan A A Status bits are reset to zero and counter is reset to word 1 a Rung is True at completion Rung Condition Enable Bit 17 Done Bit 15 Instruction Operation More than 1 Scan A A Done bit...

Page 226: ...r resets to position 001 after the last word is operated upon 1 Word Operation 1 Word Operation 1 Word Operation 1 Word Operation File Word 1 File Word 2 File Word 3 Word 14 Last Word 1st Rung Enable...

Page 227: ...emental Mode Rung Condition Enable Bit 17 Done Bit 15 Instruction Operation 1 or More Scans A A Enable bit is reset to zero B Status bits are reset to zero and counter is reset to word 1 following ope...

Page 228: ...outside the file This causes a run time error Additional programming should be used to assure that the instructions which change the instruction counter accumulated value do not cause the preset valu...

Page 229: ...t location 474 410 File A 10 words 421 474 File R 10 words 505 Instruction overview Output instruction Key sequence FILE 10 Requires 5 words of user program Can operate in incremental distributed comp...

Page 230: ...e default values Bold numbers must be replaced by user entered values The number of default address digits initially displayed 3 4 or 5 will depend on the size of the data table Initially displayed de...

Page 231: ...ion 12 5 Figure 12 13 FILE TO FILE MOVE Example Rung FILE TO FILE MOVE COUNTER ADDR 200 POSITION 001 FILE LENGTH 010 FILE A 410 421 FILE R 474 505 RATE PER SCAN 010 200 EN 17 2 DN 15 This output instr...

Page 232: ...nstruction and the corresponding instruction s which manipulate the accumulated value Do not inadvertently manipulate the preset or the accumulated values Inadvertent changes to these values could res...

Page 233: ...the instruction in the accumulated value area of the data table POSITION Current word being operated upon accumulated value of counter FILE LENGTH Number of words in file preset value of the counter F...

Page 234: ...uction transfers a duplicate of the value in a specified data table word W Figure 12 17 into a word in file R that is pointed to by the counter accumulated value Instruction overview Output instructio...

Page 235: ...be reserved for the instruction and the corresponding instruction s which manipulate the accumulated value Do not inadvertently manipulate the preset or the accumulated values Inadvertent changes to...

Page 236: ...truction in the accumulated value area of the data table POSITION Current word being operated upon accumulated value of counter FILE LENGTH Number of words in file preset value of the counter WORD ADD...

Page 237: ...s chosen when bit information is pertinent and hexadecimal display is chosen when word values are desired ASCII is chosen when character values are desired Data can be entered and or displayed in eith...

Page 238: ...version table where X 0 Binary Data Monitor 1 Hexadecimal Data Monitor 2 ASCII Data Monitor2 1 The cursor must be positioned on the file instruction in the ladder diagram 2 Requires Series B Revision...

Page 239: ...E TO FILE MOVE COUNTER ADDR 031 POSITION 001 FILE LENGTH 035 FILE A 200 242 FILE R 300 342 POSITION FILE A DATA FILE R DATA 001 A4B2 59AE 002 3C4D A23D 003 E4F6 4BC5 004 2CA3 ABC6 005 5BCF 36AE 006 F1...

Page 240: ...e data is displayed in binary representation data bits are assumed to be numbered from right to left 00 17 respectively Each column in the display represents one file In Figure 12 20 two files are sho...

Page 241: ...0 When there the field cursor is controlled by the four cursor control keys SHIFT and SHIFT If the header contains no changeable data the field cursor cannot be moved there The field cursor can be mov...

Page 242: ...ation is defined as a full screen of file words in the file section For example in Figure 12 20 a page is shown which begins at position 001 and ends at position 015 To display longer files additional...

Page 243: ...the file will not be allowed An invalid key message will appear Scrolling procedures are summarized in Table 12 C Data can always be entered or changed when the processor is in program mode In run pr...

Page 244: ...to the file word located by the Field Cursor CANCEL COMMAND Terminates Data Monitor Mode and returns display to Ladder Diagram If in On Line Data Change CANCEL COMMAND will terminate On Line Data Chan...

Page 245: ...shifted into the file and the data in the last first word of the file will be shifted up down into the output word Figure 13 1 Example of a 64 Word SHIFT FILE UP DOWN Register Starting at Word 4008 4...

Page 246: ...IFO Stack Starting at Address 4008 400 477 64 words allocated for FIFO stack 130 FIFO Load enters data into stack Input Addr 040 FIFO Unoad removes data from stack Output Addr This instruction can be...

Page 247: ...The counter address specified for the Shift File Up instruction should be reserved for that instruction Do not manipulate the counter preset or accumulated values Inadvertent change to these values c...

Page 248: ...ble FILE LENGTH Number of words in file preset value of the counter FILE Starting word of file INPUT ADDRESS Address of input word OUTPUT ADDRESS Address of output word RATE PER SCAN Number of words o...

Page 249: ...omplete mode it will take a number of scans to shift in one input word of data and to shift out one word of data to the output word The output word data should NOT be considered valid until the done b...

Page 250: ...and unload pointers will load and unload words at any point in the file The body of the file will float between these boundaries Do not expect to find any particular data entry at any specific data t...

Page 251: ...RESS Address of input word outisde the stack INPUT DATA Current data at input address 030 FL 15 Numbers shown are default values Bold numbers must be replaced by user entered values The number of defa...

Page 252: ...SHIFT REG 14 A display represented by Figure 13 5a will appear To program FIFO unload press keys SHIFT REG 15 A display represented by Figure 13 5b will appear Figures 13 6a and 13 6b show the format...

Page 253: ...ZE 064 NUMBER IN FILE 000 FILE 400 477 INPUT ADDR 130 INPUT DATA 0000 200 EN 17 200 FL 15 200 EM 14 FIFO LOAD COUNTER ADDR 200 FIFO SIZE 064 NUMBER IN FILE 000 FILE 400 477 OUTPUT ADDR 040 OUTPUT DATA...

Page 254: ...register such as shown in Figure 14 1 The user specifies the bit number to be examined and the starting address of the shift register Set Shift Bit and Reset Shift Bit are output instructions which s...

Page 255: ...Starting at Location 400 A Input Bit A Bit one of Bit Shift Register L 123 Output Bit A 32 400 401 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 L 17 16 15 14 13 12 11 10 07 06 05 04 03 02 01 00 R 17 48 402...

Page 256: ...a bit shift occurred as shown by the dotted line in Figure 14 1A The instruction operates in the complete mode The status of the input bit is shifted into the first bit in the register and the status...

Page 257: ...data table NUMBER OF BITS Number of bits in the file FILE Starting address of file INPUT Address of input bit OUTPUT Address of output bit 030 DN 15 Figure 14 3 shows the format of Figure 14 2 after t...

Page 258: ...g procedure continues throughout the stack until bit 1 is ejected from the file into a specified bit A in an output word If the shift bit register of Figure 14 1B had been 123 bits long it would have...

Page 259: ...d Bit Shift Right The procedure for using the data monitor mode for data entry or monitor is presented in Chapter 12 This condition instruction that examines a user specified bit in a bit shift regist...

Page 260: ...rned by the I O rack configuration FILE Starting address of the file file of bit shift instruction BIT NUMBER Decimal number of the bit to be examined 1 999 Figure 14 5 shows the format of Figure 14 4...

Page 261: ...ers shown are default values Bold numbers must be replaced by user entered values The number of default address digits initially displayed 3 4 or 5 will depend on the size of the data table Initially...

Page 262: ...The instruction executes upon a true rung condition NOTE If file is shifted new data in the same bit position will be set if set shift bit rung is still true Instruction overview Output instruction K...

Page 263: ...for the following condition of the bit shift register of Figure 14 1 File starts at word 4008 Bit No set bit number 67 in shift register Figure 14 1 to on 1 Figure 14 9 SET SHIFT BIT Example Rung SET...

Page 264: ...l depend on the size of the data table Initially displayed default values are governed by the I O rack configuration FILE Starting address of the file file of bit shift instruction BIT NUMBER Decimal...

Page 265: ...e some marked differences Both are block instructions that contain a counter and a file The instructions require the entry of more than one address Each has a corresponding data monitor display for mo...

Page 266: ...re 15 2 Sequencer Table Format in the Data Table Data Table Data Table 024 024 024 024 Step 001 002 Step 001 002 Step 001 002 00 01 01 01 10 10 00 00 00 01 11 01 11 00 10 10 00 01 01 11 00 11 00 11 10...

Page 267: ...row of peg locations The presence of 1 or more pegs produces a single tone or a musical chord If the cylinder wall containing the pegs could be removed cut along its axis to separate the first and las...

Page 268: ...is true This means that once the rung is enabled the counter is incremented to the next step and the data in that step will be outputted every scan that the rung remains true The instruction will not...

Page 269: ...ing bit location A 1 in a mask bit location allows the corresponding bit to be operated upon When all the output data bits are relevant to the instruction a mask of all ones should be used A mask word...

Page 270: ...counter address for the Sequencer Output instruction should be reserved for that instruction Do not manipulate the counter accumulated or preset values Inadvertent changes to these values could resul...

Page 271: ...ion in sequencer table accumulated value of counter SEQ LENGTH Number of steps preset value of counter WORDS PER STEP Width of sequencer table number of columns FILE Starting address of sequencer tabl...

Page 272: ...0 0 0 0 1 1 0 0 1 0 1 1 0 0 1 0 1 1 0 1 1 1 0 1 1 0 0 1 0 NOTE 17 16 15 14 13 12 11 10 07 06 05 04 03 02 01 00 17 16 15 14 13 12 11 10 07 06 05 04 03 02 01 00 Bit Numbers Sequencer Table Step 008 Mask...

Page 273: ...a specified word address of the instruction Figure 15 8 Example Binary Data Monitor Display of a SEQUENCER OUTPUT BINARY DATA MONITOR SEQUENCER OUTPUT COUNTER ADDR 054 STEP 008 SEQUENCER LENGTH 009 F...

Page 274: ...e address When programmed in this manner the Sequencer Input and Output instructions will track through a controlled sequence of operation The length of the sequence is equal to the number of steps in...

Page 275: ...TEP 1 FILE 110 110 MASK 010 010 Numbers shown are default values Bold numbers must be replaced by user entered values The number of default address digits initially displayed 3 4 or 5 will depend on t...

Page 276: ...puts corresponding to the specified input words less those inputs that are masked is equal to the status of all 64 bits of data in step 006 of the sequencer table the logic of the instruction is true...

Page 277: ...is loaded AC PR the done bit is set The next false to true transition of the rung condition will load the data beginning at step 1 The counter should be set to zero for start up purposes if it is desi...

Page 278: ...late the counter accumulated or preset values Inadvertent changes to these values could result in unpredictable or hazardous machine operation or run time error Damage to equipment and or personal inj...

Page 279: ...preset value of counter WORDS PER STEP Width of sequencer table number of columns FILE Starting address of sequencer table LOAD WORDS Words fetched by the instruction 030 DN 15 INPUT WORDS 1 010 3 XXX...

Page 280: ...xample Rung SEQUENCER LOAD COUNTER ADDR 0056 CURRENT STEP 008 SEQ LENGTH 012 WORDS PER STEP 4 FILE 0510 0567 0056 EN 17 0056 DN 15 INPUT WORDS 1 0111 3 0112 2 0113 4 0314 16 114 Artisan Technology Gro...

Page 281: ...ta Files A and B and place the result of the logic operation in a third File R Figure 16 1 The File Complement instruction takes the logical complement of each bit in File A and stores it in the corre...

Page 282: ...t Instruction Key sequence FILE 14 Requires 6 words of user program Can operate in incremental distributed complete or complete mode Counter is internally indexed by the instruction Programming File t...

Page 283: ...NGTH Number of words in file preset value of the counter FILE A Starting address of source file A FILE B Starting address of source file B FILE R Starting address of destination file R RATE PER SCAN N...

Page 284: ...he corresponding bit in File B If either of the bits is a 1 a 1 is stored in the corresponding bit location in File R If neither of the compared bits is a 1 a 0 is stored in File R Table 16 B Table 16...

Page 285: ...e contents of two data Files A and B and places the results of the logic operation XOR exclusive OR in a third File R The logic operation XOR compares each bit in file A to the corresponding bit in Fi...

Page 286: ...tion press keys FILE 18 The format and the technique for insertion of numbers will be identical to that of the File to File AND Figure 16 2 except that the logic operation XOR replaces AND The procedu...

Page 287: ...GTH 002 FILE A 110 110 FILE R 110 110 RATE PER SCAN 001 030 EN 17 Numbers shown are default values Bold numbers must be replaced by user entered values The number of default address digits initially d...

Page 288: ...N 17 050 DN 15 The Word to File logic instructions are Word to File AND Word to File OR Word to File EXCLUSIVE OR XOR These three instructions are output instructions which during a true rung decision...

Page 289: ...ation into the corresponding word of File R Figure 16 6 The logic operation AND compares each bit in the word to the corresponding bit in the File B word If the compared bits are both 1 a 1 is stored...

Page 290: ...e 16 7 WORD TO FILE AND Format WORD TO FILE AND COUNTER ADDR 030 POSITION 001 FILE LENGTH 001 WORD ADDR 110 FILE B 110 110 FILE R 110 110 030 DN 15 Numbers shown are default values Bold numbers must b...

Page 291: ...AND Example Rung WORD TO FILE AND COUNTER ADDR 200 POSITION 003 FILE LENGTH 006 WORD ADDR 400 FILE B 500 505 FILE R 600 605 200 DN 15 This instruction performs an OR operation on the contents of a spe...

Page 292: ...unpredictable or hazardous machine operation or run time error Damage to equipment and or personal injury could result To program a Word to File OR press keys FILE 17 The format and the technique for...

Page 293: ...Word to File XOR instruction should be reserved for the instruction and the corresponding instructions which manipulate the accumulated value Do not inadvertently manipulate the preset or accumulated...

Page 294: ...ched and a counter Figure 17 1 Upon false true transition of rung decision the input word data is compared to the file data When a match is found the position counter accumulated value indicates that...

Page 295: ...after an additional false true transition Instruction Overview Output instruction Key Sequence FILE 21 Counter is manipulated by instruction Requires 4 user program words Programming File Search Instr...

Page 296: ...of the instruction in the accumulated value area of the data table POSITION Current word being operated upon accumulated value of counter FILE LENGTH Number of words in file preset value of the counte...

Page 297: ...ransition of the rung searches the specified file File R from the XOR instruction for 1 When a 1 is found the Diagnostic instruction cross references the bit address in the file to the corresponding b...

Page 298: ...tput I O in bits 00 03 Any leading digits are stored in BCD in bits 4 7 and 10 13 Word 502 stores the rack number in bits 14 17 The module group number in bits 10 13 the high low 1 0 slot in bit 04 an...

Page 299: ...umber of default address digits initially displayed 3 4 or 5 will depend on the size of the data table Initially displayed default values are governed by the I O rack configuration COUNTER ADDRESS Add...

Page 300: ...tion will be stored in words 500 to 502 inclusive The procedure for using the data monitor for data entry or monitor is presented in Chapter 12 Figure 17 6 FILE DIAGNOSTIC Example Rung FILE DIAGNOSTIC...

Page 301: ...f they exist Moves cursor to the bit to be changed Enter a 1 to set bit ON or a 0 to set bit OFF Forcing or removing forces from input bits or output devices To terminate FORCE ON Test or Run Program...

Page 302: ...END Position cursor on TEMPORARY END instruction and press key sequence Bit monitor allows the status of all 16 bits of any data table word to be displayed Bit manipulation allows the status of the di...

Page 303: ...tput devices by overriding the I O scan An input bit can be forced on or off regardless of the actual state of the corresponding input device However forcing an output terminal will cause the correspo...

Page 304: ...erminal or processor is disconnected or loses AC power or the MODE SELECT key is pressed all force functions are cleared WARNING When an energized output is being forced off keep personnel away from t...

Page 305: ...ruction position the cursor on it and press REMOVE T END To enter a rung after the T END instruction press and then enter the new rung If the key is not pressed the rung will be inserted above the T E...

Page 306: ...hard copy printout of the program A decision must be made either to replace the error with its correct instruction see Section 4 4 4 Changing an Instruction or to remove it The ERR message due to an...

Page 307: ...dge one shot is used to set a bit on for one scan when the input condition has made a false true transition The transition represents the leading edge of the input pulse The programming for a leading...

Page 308: ...ts the trailing edge of the input pulse Programming for a trailing edge one shot is shown in Figure 19 2 Figure 19 2 Trailing Edge One Shot Input Pulse Bit 112 04 One shot Bit Bit 203 00 04 112 00 App...

Page 309: ...ressing serves two purposes it links a hardware terminal to a data table location input and it links a data table location to a terminal output In Figure A 1 reading from left to right the first numbe...

Page 310: ...ample The PLC 2 family processors at the appropriate series and revision level can address module groups in various addressing modes The term addressing mode refers to the method of hardware addressin...

Page 311: ...stall either 8 point standard density or 16 point high density used in complementary mode determines the number of bits in the words that are used You select 2 slot addressing by setting two switches...

Page 312: ...full word of the input image table 2 slot I O Group Input Terminals Input Terminals 17 16 15 14 13 12 11 10 07 06 05 04 03 02 01 00 Output image table word corresponding to the I O group unused Input...

Page 313: ...utput Terminals 17 16 15 14 13 12 11 10 07 06 05 04 03 02 01 00 Output image table word corresponding to the I O group Used Output bits Input image table word corresponding to the I O group 00 01 02 0...

Page 314: ...05 06 07 10 11 12 13 14 15 16 17 Input Terminals Output Terminals 17 16 15 14 13 12 11 10 07 06 05 04 03 02 01 00 17 16 15 14 13 12 11 10 07 06 05 04 03 02 01 00 Output image table word corresponding...

Page 315: ...one I O group is assigned to the corresponding pair of words in the input and output image tables You assign one I O rack number to eight I O groups Figure A 5 Figure A 5 I O Table and Corresponding H...

Page 316: ...See your scanner s or adapter s users manual for the specific switches and their settings The physical address of each I O group corresponds to an input and an output image table word The type of modu...

Page 317: ...the I O group 17 16 15 14 04 03 02 01 00 Input image table word corresponding to the I O group 17 16 15 14 04 03 02 01 00 Input image table word corresponding to the I O group 1 slot I O Group OR The...

Page 318: ...igit input or output instruction is associated with a particular I O module terminal Now with two I O racks you use the instruction address to identify which racks you are communicating with Figure A...

Page 319: ...ules use the lower slave bus on the I O chassis backplane for intramodule communications When you select 1 2 slot addressing the processor by way of the adapter addresses one half of an I O module slo...

Page 320: ...O module A 32 point I O module two 1 2 slot I O groups uses two input or two output words of the image table Module group 0 applies to the upper 16 points module group 1 applies to the lower 16 points...

Page 321: ...I O Group 1 Bit Bit 01 03 05 07 11 13 15 17 01 03 05 07 11 13 15 17 00 02 04 06 10 12 14 16 00 02 04 10 12 14 16 17 10 7 0 Input Word 0 Image Table Words Allocated for I O Group 0 17 10 7 0 Outut Word...

Page 322: ...ots Thus in a single 16 slot chassis you now can have four I O racks Figure A 10 Figure A 10 Assigning I O rack Numbers with 1 2 slot Addressing I O Group No 0 3 4 7 0 3 4 7 0 3 4 7 0 3 4 7 I O Groups...

Page 323: ...y the lowest group number that it occupies and at slot 0 For example a one slot block transfer module in rack 1 group 2 and 3 chassis slot 2 would be addressed by Rack Group Slot at location 120 NOTE...

Page 324: ...ot addressing See publication no 1772 2 18 for addressing information If you are communicating with a remote chassis through a 1771 ASB Series B remote I O Adapter module and the needed 1772 SD2 Remot...

Page 325: ...771 ASB Series B 8 16 32 A C X A A C A A A Legend A Any mix of modules in the respective points per module category Specific module placement with 16 point input module in one slot of a slot pair and...

Page 326: ...The value of a decimal number depends on the digits used and the place value of each digit Each place value in a decimal number represents a power of ten Figure B 1 starting with 100 The value of a de...

Page 327: ...otcal number has a certain place value represented by a power of eight Figure B 2 The decimal value of an octal number is computed by multiplying each octal digit by its place value and adding these n...

Page 328: ...nary number is computed by multiplying each binary digit by its corresponding place value and adding these numbers together By grouping several binary digits together values can be formed to represent...

Page 329: ...represent a decimal number from 0 to 9 The place values for each group of 4 digits are 20 21 22 and 23 Table B A Figure B 4 Binary Coded Decimal 0 0 1 0 0 0 1 1 1 0 0 1 10 0 x 23 0 0 x 22 0 1 x 21 2...

Page 330: ...numbers Binary coded octal BCO uses an arrangement of 8 bits one byte to represent a 3 digit octal number from 000 to 377 Figure B 5 The 8 bits are broken down into three groups 2 bits 3 bits and 3 bi...

Page 331: ...B C Numbering System Conversion Chart Hexadecimal Binary Decimal Octal 0 1 2 3 4 5 6 7 8 9 A B C D E F 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 2 3 4 5 6 7 8...

Page 332: ...ch hexadecimal digit represents 4 binary digits it is easy to convert a hexadecimal number to a binary number This is done by writing out the 4 bit pattern for each hexadecimal digit Figure B 7 Figure...

Page 333: ...apses In other words the preset value represents a specific number of increments of the time base Note however that the preset value is not an absolute length of time For example if the preset value i...

Page 334: ...preset value 100 This time interval will be greater than 0 99 seconds and less than or equal to 1 second as shown below 0 99 seconds TON timed out 1 0 second Note that special programming techniques a...

Page 335: ...considerations later on You are urged not to overspecify timing accuracy In many applications timing within 0 1 second will provide accuracy comparable to or better than typical electromechanical tim...

Page 336: ...used to operate sorting mechanisms for high speed machines Two methods can be used Method 1 The sort mechanism could be energized for example 60 msec after a reject is sensed by a particular sensor Me...

Page 337: ...ion of Immediate Input and Immediate Output instructions can compensate for the length of scan time DC Output modules typically require from 1 to 5 msec for response AC Output modules require 3 to 10...

Page 338: ...program scan The processor executes one program instruction at a time After it executes an instruction it cannot examine that instruction again until the next scan of memory With respect to timer inst...

Page 339: ...r to compensate for the length of the scan time and to assure accurate timing 10 msec timer programming must be repeated several places in the program A typical program using the total memory can nomi...

Page 340: ...hich examine the timed bit of the timer to condition an Output Energize instruction Immediate Input instructions to help assure that the timer is enabled as quickly as possible after the external even...

Page 341: ...dressed to output image table word 014 will help to assure that the output modules respond quickly to timer cycling By repeating the timer instructions and related rungs you can assure that the proces...

Page 342: ...ruction Execution Times Approximate 1 Instructions Time RTR GET BYTE 18 s L U CTR GET MCR 28 s PUT EQU LES LIMIT TEST 28 s 60 s TOF TON RTO CU CTD 83 s IMMEDIATE I O 105 s ZCL 130 s 1 These execution...

Page 343: ...shift left 14 1 bit shift right 14 5 block length 10 5 10 17 block transfer 10 1 basic operation 10 1 block transfer instructions 10 4 branch instructions 4 9 buffering data 10 12 C capabilities 1 3 c...

Page 344: ...ile XOR 16 5 file to word move 12 15 force on and force off functions 18 3 forced address display 18 4 fundamental operation 3 21 G get byte put instruction 6 8 get byte and limit test instructions 6...

Page 345: ...cer output instruction 15 4 output instructions 4 5 output override and I O update instructions 7 1 output overrides 7 1 P peripheral functions 8 1 power up recovery 2 5 processor diagnostic indicator...

Page 346: ...t instruction 15 3 sequencer table bit assignments 3 27 set shift bit 14 9 shift file down 13 5 shift file up 13 2 shift register instructions 13 1 special programming techniques 19 1 subroutine area...

Page 347: ...00 Telex 43 11 016 FAX 414 382 2400 As a subsidiary of Rockwell International one of the world s largest technology companies Allen Bradley meets today s challenges of industrial automation with over...

Page 348: ...service in house repair center WE BUY USED EQUIPMENT Sell your excess underutilized and idle used equipment We also offer credit for buy backs and trade ins www artisantg com WeBuyEquipment REMOTE IN...

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