Timer and Counter Instructions
Chapter 5
514
An individual timer or counter can time or count up to 999 intervals
or events. By cascading two or more timers or counters, the timing or
counting capability within the program can be increased beyond three
digits.
To cascade timers or counters, each timer or counter is assigned a different
word address (Figure 5.12). The status bit of the first timer (bit 15) changes
status each time the preset value is reached. The status bit of a counter
(bit 14) is set on each time a counter overflows. The status bit of the timer
or counter is then used to increment the second timer or counter and reset
the first to 000.
Figure 5.12
Cascading Counters Example
||
06
( CTU )
110 050
PR 999
AC 000
||
14
( CTU )
050 051
PR 999
AC 000
||
14
( CTR )
050 050
PR 999
AC 000
UpCount Event
Counter 050 Overflow Bit
First Increments Counter 051
Then Overflow Bit Resets Counter 050
| / |
06
110
Timer and Counter instructions are entered into memory with the processor
in the program mode.
Timer instructions are programmed by entering a word address, a time base
and a Preset Value. With the RTO instruction, the user can also enter an
Accumulated Value. The time base of 1.0 sec., 0.1 sec. or 0.01 sec. is
entered as 10, 01, or 00 respectively.
Counter instructions are programmed by entering a word address, a Preset
Value, and if desired, an Accumulated Value.
When entered, these instructions will be displayed as intensified and
blinking. The default word address above the instruction will have a
reverse-video cursor positioned at the first digit. The default word address
displayed will depend on the data table configuration (Table 5.A). Refer to
Tables 5.B and 5.C for a complete summary of the instructions.
5.3
Cascading Timers or
Counters
5.4
Programming Timer and
Counter Instructions
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