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Alinx AXU4EV-E User Manual Download Page 57

ZYNQ Ultr FPGA Board AXU4EV-E User Manual

57 / 58

Amazon Store: https://www.amazon.com/alinx

Figure 3-18-1: Carrier Board Power Schematic

The functions of each power distribution are shown in the following table:

Power

Function

+5.0V

USB power supply

+1.8V

Ethernet, USB2.0, BANK66 of Core Board

+3.3V

Ethernet, USB2.0, SD, DP, CAN, RS485

+1.2V

BANK65 of Core Board

Part 3.19: ALINX Customized Fan

Because AXU4EV-E generates a lot of heat when it works normally, we

add a heat sink and fan to the chip on the board to prevent the chip from
overheating. The control of the fan is controlled by the ZYNQ chip. The control
pin is connected to the IO of the BANK43 (AA11). If the IO level output is high,
the MOSFET is turned on and the fan is working. If the IO level output is low,
the fan stops. The fan design on the board is shown in Figure 3-19-1.

Summary of Contents for AXU4EV-E

Page 1: ...ZYNQ UltraScale FPGA Development Board AXU4EV E User Manual...

Page 2: ...ZYNQ Ultrascale FPGA Board AXU4EV E User Manual 2 58 Amazon Store https www amazon com alinx Version Record Version Date Release By Description Rev 1 0 2021 04 12 Rachel Zhou First Release...

Page 3: ...25 Part 2 8 Power Supply 26 Part 2 9 ACU4EV Core Board Size Dimension 28 Part 2 10 Board to Board Connectors pin assignment 28 Part 3 Carrier Board 37 Part 3 1 Carrier Board Introduction 37 Part 3 2...

Page 4: ...n Store https www amazon com alinx Part 3 14 EEPROM and Temperature sensor 53 Part 3 15 User LEDs 54 Part 3 16 Keys 55 Part 3 17 DIP Switch Configuration 55 Part 3 18 Power Supply 56 Part 3 19 ALINX C...

Page 5: ...I FLASH chip the PL side of the core board has 1 piece of 1GB DDR4 SDRAM chip In the design of carrier board we have extended a wealth of interfaces for users such as 1 SATA M 2 interface 1 DP interfa...

Page 6: ...programmable logic part Programmable Logic PL On the PS side and PL side of the ZU4EV chip there are 4 DDR4 and 1 DDR4 respectively each with a capacity of up to 1GB which enables the ARM system and F...

Page 7: ...f ZU4EV 4GB DDR4 PS 1GB DDR4 PL 8GB eMMC FLASH 256Mb QSPI FLASH and there are 2 crystal oscillators to provide the clock a single ended 33 3333MHz crystal oscillator for the PS system and a differenti...

Page 8: ...omputer for user debugging The serial port chip adopts the USB UAR chip of Silicon Labs CP2102GM and the USB interface adopts the MINI USB interface SD Card Slot Interface 1 Micro SD card holder used...

Page 9: ...M75 On board temperature and humidity sensor chip LM75 used to detect the temperature and humidity of the surrounding environment around the FPGA development board EEPROM One EEPROM 24LC04 with I2C in...

Page 10: ...an reach 1200MHz data rate 2400Mbps and the highest operating speed of DDR4 SDRAM on the PL side can reach 1066MHz data rate 2132Mbps In addition a 256MBit QSPI FLASH and an 8GB eMMC FLASH chip are al...

Page 11: ...th a speed of up to 1 2Ghz and supports Level 2 Cache it also contains 2 Cortex R5 processors with a speed of up to 500Mhz The ZU4EV chip supports 32 bit or 64 bit DDR4 LPDDR4 DDR3 DDR3L LPDDR3 memory...

Page 12: ...2KB level 1 instruction and data cache 1MB level 2 cache shared by 2 CPUs ARM dual core Cortex R5 processor speed up to 600MHz each CPU 32KB level 1 instruction and data cache and 128K tightly coupled...

Page 13: ...and voltage detection The main parameters of the PL logic part are as follows Logic Cells 192K Flip flops 176K Look up tables LUTs 71K Block RAM 20 6 Mb Clock Management Units CMTs 4 DSP Slices 728 Vi...

Page 14: ...he BANK64 interface of the FPGA The specific configuration of DDR4 SDRAM is shown in Table 2 3 1 below Bit Number Chip Model Capacity Factory U12 U14 U15 U16 MT40A512M16LY 062E 512M x 16bit Micron Tab...

Page 15: ...R4_DQS0_P PS_DDR_DQS_P0_504 AF21 PS_DDR4_DQS0_N PS_DDR_DQS_N0_504 AG21 PS_DDR4_DQS1_P PS_DDR_DQS_P1_504 AF23 PS_DDR4_DQS1_N PS_DDR_DQS_N1_504 AG23 PS_DDR4_DQS2_P PS_DDR_DQS_P2_504 AF25 PS_DDR4_DQS2_N...

Page 16: ...AH22 PS_DDR4_DQ10 PS_DDR_DQ10_504 AE22 PS_DDR4_DQ11 PS_DDR_DQ11_504 AD22 PS_DDR4_DQ12 PS_DDR_DQ12_504 AH23 PS_DDR4_DQ13 PS_DDR_DQ13_504 AH24 PS_DDR4_DQ14 PS_DDR_DQ14_504 AE24 PS_DDR4_DQ15 PS_DDR_DQ15...

Page 17: ...DR_DQ43_504 K24 PS_DDR4_DQ44 PS_DDR_DQ44_504 J22 PS_DDR4_DQ45 PS_DDR_DQ45_504 H22 PS_DDR4_DQ46 PS_DDR_DQ46_504 K22 PS_DDR4_DQ47 PS_DDR_DQ47_504 L22 PS_DDR4_DQ48 PS_DDR_DQ48_504 M25 PS_DDR4_DQ49 PS_DDR...

Page 18: ...S_DDR4_A6 PS_DDR_A6_504 Y22 PS_DDR4_A7 PS_DDR_A7_504 AA23 PS_DDR4_A8 PS_DDR_A8_504 AA22 PS_DDR4_A9 PS_DDR_A9_504 AB23 PS_DDR4_A10 PS_DDR_A10_504 AA25 PS_DDR4_A11 PS_DDR_A11_504 AA26 PS_DDR4_A12 PS_DDR...

Page 19: ...3 PL_DDR4_DQ5 IO_L21P_T3L_N4_AD8P_64 AE3 PL_DDR4_DQ6 IO_L20N_T3L_N3_AD1N_64 AH3 PL_DDR4_DQ7 IO_L20P_T3L_N2_AD1P_64 AG3 PL_DDR4_DQ8 IO_L18N_T2U_N11_AD2N_64 AC1 PL_DDR4_DQ9 IO_L18P_T2U_N10_AD2P_64 AB1 P...

Page 20: ...2N_T0L_N3_64 AE8 PL_DDR4_RST IO_L7P_T1L_N0_QBC_AD13P_64 AG9 PL_DDR4_CLK_N IO_L10N_T1U_N7_QBC_AD4N_64 AG5 PL_DDR4_CLK_P IO_L10P_T1U_N6_QBC_AD4P_64 AG6 PL_DDR4_CKE IO_T3U_N12_64 AE4 PL_DDR4_OTD IO_L19N_...

Page 21: ...5 MIO1_QSPI0_IO1 PS_MIO1_500 AG16 MIO2_QSPI0_IO2 PS_MIO2_500 AF15 MIO3_QSPI0_IO3 PS_MIO3_500 AH15 MIO4_QSPI0_IO0 PS_MIO4_500 AH16 MIO5_QSPI0_SS_B PS_MIO5_500 AD16 Part 2 5 eMMC Flash The ACU4EV core b...

Page 22: ...00 of the PS part of the ZYNQ UltraScale In the system design it is necessary to configure the GPIO port function of the PS side as an EMMC interface Figure 2 5 1 shows the part of eMMC Flash in the s...

Page 23: ...e clock for PS system and PL logic respectively so that PS system and PL logic can work independently The schematic diagram of the clock circuit design is shown in Figure 2 6 1 Figure 2 6 1 Core Board...

Page 24: ...nal Name Pin PS_PADI_503 N17 PS_PADO_503 N18 PS System Clock Source The X1 crystal on the core board provides a 33 333MHz clock input for the PS part The clock input is connected to the PS_REF_CLK_503...

Page 25: ...to drive the DDR4 controller and user logic circuits in the FPGA The schematic diagram of this clock source is shown in Figure 2 6 4 Figure 2 6 4 PL system clock source Clock pin assignment Signal Nam...

Page 26: ...8 Power Supply The power supply voltage of the ACU4EV core board is DC12V which is supplied by connecting the carrier board The core board uses a PMIC chip TPS6508641 to generate all the power requir...

Page 27: ...nual 27 58 Amazon Store https www amazon com alinx In addition the VCCIO power supply of BANK65 and BANK66 of XCZU4EV chip is provided by the carrier board which is convenient for users to modify but...

Page 28: ...connectors used is Panasonic AXK5A2137YG and the corresponding connector model in the carrier board is Panasonic AXK6A2337YG Among them J29 is connected to the IO of BANK65 and BANK66 J30 is connected...

Page 29: ...6 15 B65_L1_P W8 16 B65_L6_P R6 17 GND 18 GND 19 B65_L7_P L1 20 B65_L17_P N9 21 B65_L7_N K1 22 B65_L17_N N8 23 GND 24 GND 25 B65_L15_P N7 26 B65_L9_P K2 27 B65_L15_N N6 28 B65_L9_N J2 29 GND 30 GND 31...

Page 30: ...F6 88 B66_L5_P E4 89 GND 90 GND 91 B66_L4_P G3 92 B66_L2_P E1 93 B66_L4_N F3 94 B66_L2_N D1 95 GND 96 GND 97 B66_L11_P D4 98 B66_L20_P C6 99 B66_L11_N C4 100 B66_L20_N B6 101 GND 102 GND 103 B66_L12_P...

Page 31: ...32 B25_L10_P B11 33 B25_L5_P G11 34 B25_L10_N A10 35 GND 36 GND 37 B66_L18_N D9 38 B25_L12_P D12 39 B66_L18_P E9 40 B25_L12_N C12 41 GND 42 GND 43 B25_L4_N H12 44 B25_L11_P A12 45 B25_L4_P J12 46 B25...

Page 32: ...05_TX0_P E25 105 505_RX3_N A26 106 505_TX0_N E26 107 GND 108 GND 109 505_TX2_P C25 110 505_RX1_P D27 111 505_TX2_N C26 112 505_RX1_N D28 113 GND 114 GND 115 505_RX2_P B27 116 505_RX0_P F27 117 505_RX2...

Page 33: ..._L10_P W10 46 B44_L3_N AH11 47 GND 48 GND 49 B24_L11_N W11 50 B44_L1_N AH10 51 B24_L11_P W12 52 B44_L1_P AG10 53 GND 54 GND 55 B24_L9_N W13 56 B24_L4_P AE13 57 B24_L9_P W14 58 B24_L4_N AF13 59 GND 60...

Page 34: ...X0_N Y1 118 224_TX0_N W3 119 GND 120 GND Pin assignment of board to board connector J32 J32 Pin Signal Name Pin Number J32 Pin Signal Name Pin Number 1 PS_MIO35 H17 2 PS_MIO30 F16 3 PS_MIO29 G16 4 PS_...

Page 35: ...2 PS_MIO64 E19 63 PS_MIO48 J21 64 PS_MIO69 D19 65 GND 66 GND 67 PS_MIO41 J19 68 PS_MIO74 D20 69 PS_MIO32 J16 70 PS_MIO73 G21 71 GND 72 GND 73 PS_MIO46 L20 74 PS_MIO72 G20 75 PS_MIO50 M19 76 PS_MIO71 B...

Page 36: ...ZYNQ Ultrascale FPGA Board AXU4EV E User Manual 36 58 Amazon Store https www amazon com alinx 111 12V 112 12V 113 12V 114 12V 115 12V 116 12V 117 12V 118 12V 119 12V 120 12V...

Page 37: ...ction you can understand the function of the carrier board part 1 Channel M 2 interface 1 Channel DP output interface 4 USB 3 0 Interfaces 2 Channel 10 100M 1000M Ethernet RJ 45 interface 2 Channel US...

Page 38: ...nication speed of up to 6Gbps The M 2 interface uses the M key slot which only supports PCI E not SATA When users choose SSD solid state drives they need to choose PCIE type SSD solid state drives The...

Page 39: ...E_RSTn_MIO37 PS_MIO37_501 J17 PCIE Reset Signal Part 3 3 DP Interface The AXU4EV E development board has a standard DisplayPort output display interface for video image display The interface supports...

Page 40: ...Positive GT0_DP_TX_N 505_TX3_N B24 Low bits of DP Data Transmit Negative GT1_DP_TX_P 505_TX2_P C25 High bits of DP Data Transmit Positive GT1_DP_TX_N 505_TX2_N C26 High bits of DP Data Transmit Negati...

Page 41: ...data communication The USB interface is a flat USB interface USB Type A which is convenient for users to connect different USB Slave peripherals such as USB mouse keyboard or U disk at the same time T...

Page 42: ...HY chip uses Micrel s KSZ9031RNX Ethernet PHY chip to provide users with network communication services The KSZ9031RNX chip supports 10 100 1000 Mbps network transmission rate and communicates with th...

Page 43: ...ated through RMII bus and the transmission clock is 25Mhz Data is sampled on the rising edge and falling samples of the clock Figure 3 5 1 ZYNQ PS system and GPHY connection diagram The Gigabit Ethern...

Page 44: ...rnet 1 Receive Data Bit3 PHY1_RXCTL PS_MIO75 A19 Ethernet 1 Receive Enable Signal PHY1_MDC PS_MIO76 B20 Ethernet 1 MDIO Clock Management PHY1_MDIO PS_MIO77 F20 Ethernet 1 MDIO Management Data PHY2_TXC...

Page 45: ...perating system kernel the file system and other user data files The SDIO signal is connected to the IO signal of the PS BANK501 of ZU4EV Since the VCCMIO of the BANK is set to 1 8V but the data level...

Page 46: ...Data3 SD_CD PS_MIO45 K20 SD card insertion signal Part 3 8 Expansion Header The AXU4EV E board is reserved with two 0 1 inch standard pitch 40 pin expansion ports J45 and J46 which are used to connect...

Page 47: ...L4_N H12 24 B45_L4_P J12 25 B46_L11_N J14 26 B46_L11_P K14 27 B46_L10_N H13 28 B46_L10_P H14 29 B46_L7_N F13 30 B46_L7_P G13 31 B46_L9_N G14 32 B46_L9_P G15 33 B46_L5_N D14 34 B46_L5_P D15 35 B46_L1_N...

Page 48: ...C12 35 B44_L7_N AB13 36 B44_L7_P AA13 37 GND 38 GND 39 3 3V 40 3 3V Part 3 9 CAN communication interface There are 2 CAN communication interfaces on the AXU4EV E carrier board which are connected to t...

Page 49: ...communication interface There are two 485 communication interfaces on the AXU4EV E carrier board The 485 communication port 1 is connected to the IO interface of BANK43 45 on the PL system The 485 tr...

Page 50: ...annel 485 Transmit Enable Part 3 11 MIPI camera interface The AXU4EV E carrier board includes a MIPI camera interface which can be used to connect with the ALINX Brand MIPI OV5640 camera module AN5641...

Page 51: ...MIPI_LAN1_N B65_L3_N V8 MIPI Input Date LANE1 Negative CAM_GPIO B43_L4_P AE10 GPIO Control of Camera CAM_CLK B43_L4_N AF10 Clock Input of Camera CAM_SCL B43_L11_P Y9 I2C Clock of Camera CAM_SDA B43_L...

Page 52: ...clock to provide an accurate clock source to the internal clock circuit so that the RTC can accurately provide clock information At the same time in order for the real time clock to operate normally...

Page 53: ...ch is connected to the PS terminal through the I2C bus A high precision low power digital temperature sensor chip is installed on the AXU4EV E FPGA development board and the model is LM75 from ON Semi...

Page 54: ...e and 1 User LED Controlled by PL side The user can control the user LED on and off through the program When the IO voltage of the connected user LED light is low the user LED light is off and when th...

Page 55: ...reset KEY and the user KEYs are both low level active The connection diagram of the user key is shown in Figure 3 16 1 Figure 3 16 1 Rest keys connection diagram ZYNQ pin assignment of keys Signal Nam...

Page 56: ...ODE 3 0 Start mode ON ON ON ON 0000 PS JTAG ON ON OFF ON 0010 QSPI FLASH ON OFF ON OFF 0101 SD Card ON OFF OFF ON 0110 EMMC Part 3 18 Power Supply The power input voltage of the AXU4EV E development b...

Page 57: ...D DP CAN RS485 1 2V BANK65 of Core Board Part 3 19 ALINX Customized Fan Because AXU4EV E generates a lot of heat when it works normally we add a heat sink and fan to the chip on the board to prevent t...

Page 58: ...inx Figure 3 16 1 Fan Design Schematic The fan has been screwed to the AXUEG FPGA development board before leaving the factory The power of the fan is connected to the socket of J24 The red is positiv...

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