ZYNQ Ultr FPGA Board AXU4EV-E User Manual
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JTAG debugging interface
1-Channel temperature sensor
1-Channel EEPROM
1-Channel RTC real-time clock
3 LED lights
3 Keys
Part 3.2: M.2 Interface
The AXU4EV-E development board is equipped with a PCIE x1 standard
M.2 interface for connecting M.2 SSD solid state drives, with a communication
speed of up to 6Gbps. The M.2 interface uses the M key slot, which only
supports PCI-E, not SATA. When users choose SSD solid state drives, they
need to choose PCIE type SSD solid state drives.
The PCIE signal is directly connected to the BANK505 PS MGT
transceiver of ZU4EV, and the TX signal and RX signal of one channel are
connected to the LANE1 of MGT in a differential signal mode. The PCIE clock
is provided by the Si5332 chip, the frequency is 100Mhz, and the schematic
diagram of the M.2 circuit design is shown in Figure 3-2-1:
Figure 3-2-1: M.2 Interface Schematic