ZYNQ Ultr FPGA Board AXU4EV-E User Manual
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Figure 2-6-2: Passive Crystal Oscillator for RTC
Clock pin assignment:
Signal Name
Pin
PS_PADI_503
N17
PS_PADO_503
N18
PS System Clock Source
The X1 crystal on the core board provides a 33.333MHz clock input for the
PS part. The clock input is connected to the PS_REF_CLK_503 pin of
BANK503 of the ZYNQ chip. The schematic diagram is shown in Figure 2-6-3:
Figure 2-6-3: Active Crystal in PS part
Clock pin assignment:
Signal Name
Pin
PS_CLK
R16