ZYNQ Ultr FPGA Board AXU4EV-E User Manual
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MMC_DAT7
PS_MIO20_500
AD19
MMC_CMD
PS_MIO21_500
AC21
MMC_CCLK
PS_MIO22_500
AB20
MMC_RSTN
PS_MIO23_500
AB18
Part 2.6: Clock configuration
The core board provides reference clock and RTC real-time clock for PS
system and PL logic respectively, so that PS system and PL logic can work
independently. The schematic diagram of the clock circuit design is shown in
Figure 2-6-1:
Figure 2-6-1: Core Board Clock Source
PS System RTC Real Time Clock
The passive crystal Y2 on the core board provides a 32.768KHz real-time
clock source for the PS system. The crystal is connected to the PS_PADI_503
and PS_PADO_503 pins of BANK503 of the ZYNQ chip. The schematic
diagram is shown in Figure 2-6-2: