ZYNQ FPGA Core Board AC7Z100B User Manual
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www.alinx.com
U4,U5,U7,U8
MT41J256M16HA-125
256M x 16bit
Micron
Table 3-1: DDR3 SDRAM Configuration
The hardware design of DDR3 requires strict consideration of signal
integrity. We have fully considered the matching resistor/terminal resistance,
trace impedance control, and trace length control in circuit design and PCB
design to ensure high-speed and stable operation of DDR3.
Figure 3-1: The Schematic Part of DDR3 DRAM on the PS side
