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Alinx AC7Z100B, User Manual

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Alinx AC7Z100B User Manual Download Page 24

ZYNQ FPGA Core Board AC7Z100B User Manual

24 / 32

www.alinx.com

Part 10: AC7Z100B Core Board Size Dimension

Figure 10-1: AC7Z100B Core Board Size Dimension

Part 11: Board to Board Connectors Pin
Assignment

The core board has a total of four high-speed expansion ports. It uses four

120-pin inter-board connectors (J29~J32) to connect to the carrier board. The
connector uses the Panasonic AXK5A2147YG, and the connector type
corresponding to the carrier board is AXK6A2337YG. J29 connects BANK10 IO
and BANK11 IO, J30 connects GTX transceiver signal, J31 connects JTAG and
BANK35 IO (1.8V level standard), J32 connects PS MIO, IO and +5V power
supplies of the BANK11, BANK12

Pin assignment of J29 connector

Summary of Contents for AC7Z100B

Page 1: ...ZYNQ7000 FPGA Core Board AC7Z100B System on Module...

Page 2: ...ZYNQ FPGA Core Board AC7Z100B User Manual 2 32 www alinx com Version Record Version Date Release By Description Rev 1 0 2020 06 28 Rachel Zhou First Release...

Page 3: ...Z100B Core Board Introduction 4 Part 2 ZYNQ Chip 5 Part 3 DDR3 DRAM 8 Part 4 QSPI Flash 14 Part 5 eMMC Flash 16 Part 6 Clock Configuration 17 Part 7 LED Light 20 Part 8 Reset circuit 21 Part 9 Power S...

Page 4: ...at speeds up to 800MHz data rate 1600Mbps In addition two 256MBit QSPI FLASH and 8GB eMMC FLASH chips are integrated on the core board to boot the storage configuration and system files In order to co...

Page 5: ...AC7Z100B Core Board Rear View Part 2 ZYNQ Chip The FPGA core board AC7Z100B uses Xilinx s Zynq7000 series chip module XC7Z100 2FFG900 The chip s PS system integrates two ARM Cortex A9 processors AMBA...

Page 6: ...Block Diagram of the ZYNQ7000 Chip The main parameters of the PS system part are as follows ARM dual core CortexA9 based application processor ARM v7 architecture up to 800MHz 32KB level 1 instructio...

Page 7: ...re as follows Logic Cells 444K Look up tables LUTs 277440 Flip flops 554 800 18x25MACCs 2020 Block RAM 26 5Mb 16 channel high speed GTX transceiver supporting PCIE Gen2x8 Two AD converters for on chip...

Page 8: ...vely Two DDR3 SDRAMs form a 32 bit bus width The PS side DDR3 SDRAM has a maximum operating speed of 533MHz data rate 1066Mbps and two DDR3 memory systems are directly connected to the memory interfac...

Page 9: ...ation The hardware design of DDR3 requires strict consideration of signal integrity We have fully considered the matching resistor terminal resistance trace impedance control and trace length control...

Page 10: ...S_DDR3_DQS4_N PS_DDR_DQS_N3_502 L29 PS_DDR3_D0 PS_DDR_DQ0_502 A25 PS_DDR3_D1 PS_DDR_DQ1_502 E25 PS_DDR3_D2 PS_DDR_DQ2_502 B27 PS_DDR3_D3 PS_DDR_DQ3_502 D25 PS_DDR3_D4 PS_DDR_DQ4_502 B25 PS_DDR3_D5 PS_...

Page 11: ...502 M30 PS_DDR3_DM0 PS_DDR_DM0_502 C27 PS_DDR3_DM1 PS_DDR_DM1_502 B30 PS_DDR3_DM2 PS_DDR_DM2_502 H29 PS_DDR3_DM3 PS_DDR_DM3_502 K28 PS_DDR3_A0 PS_DDR_A0_502 L25 PS_DDR3_A1 PS_DDR_A1_502 K26 PS_DDR3_A2...

Page 12: ...Pin Name ZYNQ Pin Number PL_DDR3_DQS0_P IO_L3P_T0_DQS_33 K3 PL_DDR3_DQS0_N IO_L3N_T0_DQS_33 K2 PL_DDR3_DQS1_P IO_L9P_T1_DQS_33 J1 PL_DDR3_DQS1_N IO_L9N_T1_DQS_33 H1 PL_DDR3_DQS2_P IO_L15P_T2_DQS_33 E...

Page 13: ...23P_T3_33 C2 PL_DDR3_D25 IO_L22N_T3_33 A2 PL_DDR3_D26 IO_L19P_T3_33 B4 PL_DDR3_D27 IO_L20N_T3_33 B5 PL_DDR3_D28 IO_L24P_T3_33 C1 PL_DDR3_D29 IO_L20P_T3_33 A3 PL_DDR3_D30 IO_L24N_T3_33 C4 PL_DDR3_D31 I...

Page 14: ...R3_CLK0_N IO_L21N_T3_DQS_34 D8 PL_DDR3_CKE IO_L24P_T3_34 D6 Part 4 QSPI Flash The FPGA core board AC7Z100B is equipped with two 256MBit Quad SPI FLASH chips to form an 8 bit bandwidth data bus the fla...

Page 15: ...n the schematic Figure 4 1 QSPI Flash in the schematic Configure chip pin assignments Signal Name ZYNQ Pin Name ZYNQ Pin Number QSPI0_SCK PS_MIO6_500 D24 QSPI0_CS PS_MIO1_500 D23 QSPI0_D0 PS_MIO2_500...

Page 16: ...LASH it can be used as a large capacity storage device for the ZYNQ system such as ARM applications system files and other user data files The specific models and related parameters of eMMC FLASH are...

Page 17: ...Part 6 Clock Configuration The core system provides a reference clock for the PS system the PL logic section and the GTX transceiver allowing the PS system and PL logic to work independently The schem...

Page 18: ...gram is shown in Figure 6 2 Figure 6 2 Active crystal oscillator to the PS section PS Clock Pin Assignment Signal Name ZYNQ Pin PS_CLK A22 PL system clock source The differential 200MHz PL system cloc...

Page 19: ...nt Signal Name ZYNQ Pin SYS_CLK_P F9 SYS_CLK_N E8 GTX reference clock The FPGA core board AC7Z100B provides a 125Mhz reference clock for the GTX transceiver The reference clock is connected to the ref...

Page 20: ...BANK111_CLK1_P AC8 BANK111_CLK1_N AC7 Part 7 LED Light There are 2 red LED lights on the AC7Z100B FPGA core board one of which is the power indicator light PWR one is the configuration LED light DONE...

Page 21: ...gnal is connected to the reset button on the carrier board The reset output is connected to the PS reset pin of the ZYNQ chip The user can use the buttons on the carrier board to reset the ZYNQ system...

Page 22: ...by a connection carrier board The power supply design diagram on the FPGA board is shown in Figure 9 1 Figure 9 1 Power interface section in the schematic 5V generates 1 0V ZYNQ core power through DCD...

Page 23: ...Supply Function 1 0V ZYNQ PS and PL section Core Voltage 1 8V ZYNQ PS and PL partial auxiliary voltage BANK501 BANK35 eMMC 3 3V ZYNQ Bank0 Bank500 QSIP FLASH Clock Crystal 1 5V DDR3 ZYNQ Bank502 Bank3...

Page 24: ...ed expansion ports It uses four 120 pin inter board connectors J29 J32 to connect to the carrier board The connector uses the Panasonic AXK5A2147YG and the connector type corresponding to the carrier...

Page 25: ...N AH24 20 B11_L16_N AK18 21 B11_L5_P AH23 22 B11_L16_P AK17 23 GND 24 GND 25 B11_L15_P AJ20 26 B11_L6_N AH22 27 B11_L15_N AK20 28 B11_L6_P AG22 29 GND 30 GND 31 B11_L13_N AH21 32 B11_L17_N AJ19 33 B11...

Page 26: ...N AC16 83 GND 84 GND 85 B10_L14_N AG15 86 B10_L12_P AF14 87 B10_L14_P AF15 88 B10_L12_N AG14 89 GND 90 GND 91 B10_L1_P AK13 92 B10_L22_P AB15 93 B10_L1_N AK12 94 B10_L22_N AB14 95 GND 96 GND 97 B10_L8...

Page 27: ...111_RX3_N AA3 21 BANK111_TX3_P V2 22 BANK111_RX3_P AA4 23 GND 24 GND 25 BANK111_CLK0_N U7 26 BANK111_CLK1_N W7 27 BANK111_CLK0_P U8 28 BANK111_CLK1_P W8 29 GND 30 GND 31 BANK112_TX0_N T1 32 BANK112_RX...

Page 28: ...BANK110_TX1_P AF2 83 GND 84 GND 85 BANK109_TX2_P AJ4 86 BANK110_RX2_N AF5 87 BANK109_TX2_N AJ3 88 BANK110_RX2_P AF6 89 GND 90 GND 91 BANK109_TX3_P AK2 92 BANK110_TX2_N AE3 93 BANK109_TX3_N AK1 94 BANK...

Page 29: ...L22_N B11 20 B35_L5_P K15 21 B35_L22_P C11 22 B35_L5_N J15 23 GND 24 GND 25 B35_L20_N B12 26 B35_L10_P F13 27 B35_L20_P C12 28 B35_L10_N E12 29 GND 30 GND AA12 31 B35_L19_N C13 32 B35_L12_N F14 33 B35...

Page 30: ...B16 69 B35_L15_P F17 70 B35_L17_P C17 71 GND 72 GND 73 B35_L7_N G16 74 75 B35_L7_P G17 76 77 GND 78 GND 79 B35_L6_N H16 80 81 B35_L6_P J16 82 83 GND 84 GND 85 86 87 88 89 GND 90 GND 91 92 93 94 95 GND...

Page 31: ...D 18 GND 19 PS_MIO7 B24 20 PS_MIO26 M17 21 22 PS_MIO25 G19 23 GND 24 GND 25 PS_MIO40 B20 26 PS_MIO24 M19 27 PS_MIO41 J18 28 PS_MIO23 J21 29 GND 30 GND 31 PS_MIO42 D20 32 PS_MIO27 G20 33 PS_MIO43 E18 3...

Page 32: ...12_L15_N AG29 80 B12_L7_N AD26 81 B12_L15_P AF29 82 B12_L7_P AC26 83 GND 84 GND 85 B11_L23_N AA23 86 B11_L11_P AD23 87 B11_L23_P AA22 88 B11_L11_N AE23 89 GND 90 GND 91 B11_L21_N Y23 92 B11_L9_P AF23...

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