ZYNQ FPGA Core Board AC7Z100B User Manual
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Figure 6-3: PL system clock source
PL Clock pin assignment:
Signal Name
ZYNQ Pin
SYS_CLK_P
F9
SYS_CLK_N
E8
GTX reference clock
The FPGA core board AC7Z100B provides a 125Mhz reference clock for
the GTX transceiver. The reference clock is connected to the reference clock
input REFCLK1P/REFCLK1N of the BANK111. The schematic diagram of the
clock source is shown in Figure 6-4.
