Pin No.
Pin Name
I/O
Description
-58-
IC DESCRIPTION -5/5 (NDV8601 -5/7)
157
AD[15]
B
µP multiplexed address/data bus 15
158
AD[14]
B
µP multiplexed address/data bus 14
159
VDD
P
Core Power=1.8V
160
SCLK
O
External bus clock used for programmable host bus peripherals
161
ACK
B
Programmable WAIT-/ACK-/RDY- control
162
VSSIO
P
I/O Pad ground
163
AD[13]
B
µP multiplexed address/data bus 13
164
AD[12]
B
µP multiplexed address/data bus 12
165
AD[11]
B
µP multiplexed address/data bus 11
166
AD[10]
B
µP multiplexed address/data bus 10
167
AD[9]
B
µP multiplexed address/data bus 9
168
AD[8]
B
µP multiplexed address/data bus 8
169
VDDIO
P
I/O Pad power=3.3V
170
PWE[1]
B
Byte write enable for FLASH, Electrically Erasable Programmable Read-Only Memory (EEPROM),
static random access memory (SRAM) or peripherals
171
VSS
P
Core and Ring Ground
172
AD[7]
B
µP multiplexed address/data bus 7
173
AD[6]
B
µP multiplexed address/data bus 6
174
AD[5]
B
µP multiplexed address/data bus 5
175
AD[4]
B
µP multiplexed address/data bus 4
176
AD[3]
B
µP multiplexed address/data bus 3
177
VSSIO
P
I/O Pad ground
178
AD[2]
B
µP multiplexed address/data bus 2
179
AD[1]
B
µP multiplexed address/data bus 1
180
AD[0]
B
µP multiplexed address/data bus 0
181
VDDIO
P
I/O Pad power=3.3V
182
PWE[0]
B
Byte write enable for FLASH, Electrically Erasable Programmable Read-Only Memory (EEPROM),
static random access memory (SRAM) or peripherals
ALE
Latched Address 0
Latched Address 1
Latched Address 2
Latched Address 3
I/O Pad ground
Read
190
LHLDA
O
Bus Hold Acknowledge in slave mode
191
LHLD
I
Bus Hold Request from external master in slave mode
192
VDD
P
Core Power=1.8V
193
PCS0
O
Peripheral chip select 0, generally used for enabling the program store read-only memory (ROM)/
FLASH
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