Aiwa XD-PG700, Service Manual

Page: 50 / 78

Pin No. Pin Name I/O Description
-50-
IC DESCRIPTION -4/5 (HDC25D811B -3/6)
83 CAPT2 - DAC Top Coupling Cap Port for DAC 2
84 AOUT1 O SERVO D/A OUT1
85 AGND - AGND : DAC10BIT
86 AGND - AGND : DAC10BIT
87 CAPT1 - DAC Top Coupling Cap Port for DAC 1
88 AOUT0 O SERVO D/A OUT0
89 CAPT0 - DAC Top Coupling Cap Port for DAC 0
90 ADCVCM I ADC Swing Reference (AVDD/2) (use 1uF,10pF Cap)
91 VREFN I ADC bottom voltage
92 VREFP I ADC top voltage
93 CH0 I ADC Input channel 0
94 CH1 I ADC Input channel 1
95 CH2 I ADC Input channel 2
96 CH3 I ADC Input channel 3
97 CH4 I ADC Input channel 4
98 AGND - AGND : ADC10BIT
99 AGND - AGND : ADC10BIT
100 CH5 I ADC Input channel 5
101 AVDD - AVDD : ADC10BIT
102 AVDD - AVDD : ADC10BIT
103 REFBIAS1 I Test pin for adjusting the bias level, expected = 2.1V
104 REF I ADC REF BIAS
105 TESTOUT15 I/O TEST OUT (Default 0)
106 TESTOUT14 I/O TEST OUT (Default 0)
107 TESTOUT13 I/O TEST OUT (Default 0)
108 TESTOUT12 I/O TEST OUT (Default 0)
109 TESTOUT11 I/O TEST OUT (Default 0)
110 TESTOUT10 I/O TEST OUT (Default 0)
111 GND - GND
112 RAMTO7 O Internal RAM Test Out
113 RAMTO6 O Internal RAM Test Out
114 RAMTO5 O Internal RAM Test Out
115 RAMTO4 O Internal RAM Test Out
116 RAMTO3 O Internal RAM Test Out
117 RAMTO2 O Internal RAM Test Out
118 RAMTO1 O Internal RAM Test Out
119 RAMTO0 O Internal RAM Test Out
120 VDD - VDD
121 SENS O SERVO DSP INTERNAL STATUS MONITOR
122 VDD - VDD : PLL
123 LRCK O Audio DAC FS Output
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