Aiwa XD-PG700, Service Manual

Page: 54 / 78

Pin No. Pin Name I/O Description
-54-
IC DESCRIPTION -5/5 (NDV8601 -1/7)
1 VDDIO P I/O Pad power=3.3V
2 MD[10] B SDRAM data bus 10
3 MD[11] B SDRAM data bus 11
4 VDD P Core Power=1.8V
5 MD[12] B SDRAM data bus 12
6 VSSIO P I/O Pad ground
7 MD[13] B SDRAM data bus 13
8 MD[14] B SDRAM data bus 14
9 MD[15] B SDRAM data bus 15
10 VDDIO P I/O Pad power=3.3V
11 DQM[1] O SDRAM data byte enables 1
12 MA[9] O SDRAM address bus 9
13 MA[8] O SDRAM address bus 8
14 VSSIO P I/O Pad ground
15 MA[7] O SDRAM address bus 7
16 MA[6] O SDRAM address bus 6
17 VSS P Core and Ring Ground
18 MA[5] O SDRAM address bus 5
19 VDDIO P I/O Pad power=3.3V
20 MA[4] O SDRAM address bus 4
21 MA[3] O SDRAM address bus 3
22 MCLK O SDRAM clock
23 VSSIO P I/O Pad ground
24 CKE O SDRAM Clock Enable
25 MA[2] O SDRAM address bus 2
26 MA[1] O SDRAM address bus 1
27 VDDIO P I/O Pad power=3.3V
28 MA[0] O SDRAM address bus 0
29 MA[10] O SDRAM address bus 10
30 MA[11] O SDRAM address bus 11
31 VSSIO P I/O Pad ground
32 MA[12] O SDRAM address bus, reserved for pin compatibility with 64-Mb SDRAM
33 MA[13] O SDRAM address bus, reserved for pin compatibility with 64-Mb SDRAM
34 VDD P Core Power=1.8V
35 CS0 O SDRAM primary bank chip select
36 VDDIO P I/O Pad power=3.3V
37 RAS O SDRAM
38 CAS O SDRAM
39 WE O SDRAM
40 VSSIO P I/O Pad ground
41 DQM[0] O SDRAM data byte enables 0
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