Pin No.
Pin Name
I/O
Description
-45-
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
CKE
CLK
UDQM
NC
VCCQ
MD8
MD9
VSSQ
MD10
MD11
VCCQ
MD12
MD13
VSSQ
MD14
MD15
GND
I
I
I
–
–
I/O
–
I/O
–
I/O
–
I/O
–
This pin determines whether or not the next CLK is valid. If CKE is High, the next CLK rising
edge is valid. If CKE is Low, the next CLK rising edge is invalid. This pin is used for power-
down and clock suspend modes.
CLK is the master clock input to this pin. The other input signals are referred at CLK rising edge.
DQM controls input/output buffers.
- Read operation: If DQM is High, The output buffer becomes High-Z. If the DQM is Low, the
output buffer becomes Low-Z.
- Write operation: If DQM is High, the previous data is held (the new data is not written). If
DQM is Low, the data is written.
Not used
3.3 V is applied. (VCCQ is for the output buffer.)
Data is input and ouput from these pins. These pins are the same as those of a conventional
DRAM.
Ground is connected. (VSSQ is for the output buffer.)
Data is input and ouput from these pins. These pins are the same as those of a conventional
DRAM.
3.3 V is applied. (VCCQ is for the output buffer.)
Data is input and ouput from these pins. These pins are the same as those of a conventional
DRAM.
Ground is connected. (VSSQ is for the output buffer.)
Data is input and ouput from these pins. These pins are the same as those of a conventional
DRAM.
Ground is connected. (VSS is for the internal circuit.)
IC DESCRIPTION -2/5 (M12L16161A-7T -2/2)
www. xiaoyu163. com
QQ 376315150
9
9
2
8
9
4
2
9
8
TEL 13942296513
9
9
2
8
9
4
2
9
8
0
5
1
5
1
3
6
7
3
Q
Q
TEL 13942296513 QQ 376315150 892498299
TEL 13942296513 QQ 376315150 892498299
