Aim AXC-FDX-2, Hardware Manual

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4 . Technical Data
AXC-FDX-2 Hardware Manual 18
Time Tagging: For absolute time tagging, a special time code processor
implements an IRIG-B encoder/decoder. If no external IRIG-B source is available a time
code in IRIG B format is generated and can be used to synchronize multiple boards or
modules.
Decoder:
Format: IRIG-B-122
Resolution: 100ns
Width: 1 Year (46 Bit)
Signal Waveform: Amplitude modulated sine wave or square wave
Modulation Ratio: 3:1 to 6:1
Input Amplitude: 0.6V
p-p
to 5V
p-p
Input Impedance: > 10k ohm
Coupling: AC coupled
Time Jitter: +/- 5µs (depending on the input signal quality)
Lock time: < 5s
Freewheeling accuracy after 10 Minutes < 1ppm (assuming input
signal accuracy better than 50ppm)
Encoder:
Format: IRIG-B-122
Absolute Accuracy: +/-25ppm (standard Oscillator)
Signal Waveform: Amplitude modulated sine wave
Output Amplitude: ~ 4.5 V
p-p,
High voltage level
Output Impedance: ~ 51 ohm
Coupling: AC coupled
Modulation Ratio: ~ 3 : 1
Carrier Frequency: 1kHz +/-50ppm
Physical Bus Interface
:
The Board implements two Physical Ports for 10/100/1000 Mbit/s
AFDX network
Connectors:
Gigabit (10/100/1000Mbit) Ethernet RJ45 connector
15 pol. DSUB female 3-row high density for Trigger, Discrete and
IRIG-B/RS422 signals
USB connector for maintenance purposes
3Pin Through-Hole header for maintenance purposes
Through-Hole Micro Header for maintenance purposes
XMC connector P15 for single Lane 5Gb/s PCI Express Bus
Rear I/O over P14 PMC connector
Trigger In: TTL compatible Input Level and fast ESD protection diodes.
Additional varistors on the Front IO nearby connector to suppress
peaks of glitches. Rising Edge sensitive, Pulse width > 75 ns