Aim AXC-FDX-2, Hardware Manual

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3 . Structure of the AXC-FDX-2
AXC-FDX-2 Hardware Manual 11
3.1 System on Chip (SoC)
The main part of the design is implemented within a SoC of the latest generation. This
SoC contains a Dual-Core RISC Processor running at up to 800 MHz, dedicated
hardware interfaces like DDR3 RAM controller, a PCIe 2.0 Endpoint and several
programmable interfaces for communication and memory attachment.
Additionally, a large programmable logic is directly attached to the Processing System
within this SoC, so fast access from the processor to the programmable logic is
guaranteed.
3.1.1 Ethernet MAC Features
The Programmable Logic contains two fully independent AFDX- specific MAC´s. Each
can receive and transmit fully compliant AFDX frames.
The decoder in each MAC receives, analyses and stores data with a data rate of up to
1000 MBit per second. The gap between two frames is measured with a resolution of
8ns at 1000Mbit/s, 40ns at 100 MBit/s and 400ns at 10 MBit/s. Minimum possible gap
time is 48 ns in 1000Mbit operation mode, 480ns for 100Mbit and 4,8us for 10Mbit.
Each received message is checked for errors in the MAC header and the IP header and
for errors on the physical bus.
The transmitter operates fully independent from the receiver. The transmitter is capable
of generating data independent from the BIU Processor, time tag insertion as payload
and error generation. Additionally, each frame can be started on several events like
inter frame spacing, trigger events, absolute time or on packet group wait timing.
Redundant operation of receiver and transmitter is also supported with additional
features like individual frame skew between the two ports.
3.1.2 PCI-Express Bus and DMA Engine
The FPGA architecture of AIM´s family of PCI Express based modules includes as Host
Interface a 1-lane PCIe 2.0 endpoint that provide 500 Mbyte/s upstream and
downstream bandwidth, concurrently. This State-of-the-Art Interface is commonly used
in modern PC Systems and provides enough performance to reach the necessary
bandwidth for the two 1GBit Ethernet Interfaces.
The FPGA logic includes independent DMA units for each Transmitter and Receiver.
The DMA engine will transfer TX data from Host memory to On-Board memory and
Receiver data from On-Board memory to Host memory. This is done fully independent
from any processor interaction to ensure maximum performance.