Aim AXC-FDX-2, Hardware Manual

Page: 21 / 31

3 . Structure of the AXC-FDX-2
AXC-FDX-2 Hardware Manual 13
3.1.4 Application Specific Processor
Core 1 of the Dual Core Processor acts as Application Specific Processor and runs an
embedded Linux operating system.
The ASP performs the followed main tasks:

Setup of the SoC resources (DDR3 RAM, MMU, PCIe etc.)

Load Programmable Logic and starts second BIU core

Setup Receive and Transmit DMA machines in the PL

Relieve the Host system, fasten up the board and expands the capability of the
AXC-FDX-2 module to a high level instrument.
3.1.5 BIU Processor
Core 2 of the Dual Core Processor is used as Bus Interface Processor (BIP) and
handles the real time critical control of the two AFDX ports.
The BIP performs the following tasks:

Execute a Frontend Selftest on Power Up

Service the AFDX-MAC to handle the bus traffic in real time

Support the ASP with Pre-Filtering and Analysis of received data

Support special transmit modes like redundant transmit or Simulation mode
3.1.6 Memory Interface
The SoC has a dedicated 1GByte DDR3 RAM directly attached to it, storing the
executable code and application specific data buffering. Due to its close attachment
over several AXI Bus Interfaces to the programmable logic, the access latency is
minimized.
For 1000Mbit Mode an additional 2GByte DDR3 RAM is available to extend the
recording capability. This memory is solely used by the MAC for storing receiver data.
3.2 Gigabit Ethernet Phyter
The Frontend Interface is realised using a Gigabit Ethernet Phyter of the latest
generation. Besides the Ethernet specific sender and receiver features, the Phyter offer
automatic MDI/MDIX crossover at all speeds of operation, different selftest features,
and a powerful frontend interface for reaching highest cable length.
In standard mode, the Auto negotiation is switched of, and the speed is user selectable
via software. If necessary the Auto negotiation can be switched on via software.