85
State/Timing Modules Specifications and
Characteristics
Key Specifications* and Characteristics
Agilent Model Number
16715A, 16716A, 16717A
16740A, 16741A, 16742A
16750A, 16751A, 16752A
16760A
Maximum state acquisition rate on
16715A, 16716A: 167 Mb/s
200 Mb/s
400 Mb/s [1]
Full channel: 800 Mb/s
each channel
16717A, 333 Mb/s [1]
Half channel: 1.25 Gb/s
Maximum timing sample rate
Timing Zoom: 2 GHz (16716A,
Timing Zoom: 2 GHz
Timing Zoom: 2 GHz
Conventional: 800 MHz
(half/full channel)
16717A only)
Conventional: 800/400 MHz
Conventional: 800/400 MHz
Transitional: 400 MHz
Conventional: 667/333 MHz
Transitional: 400 MHz
Transitional: 400 MHz
Transitional: 333 MHz
Channels/module
68
68
68
34
Maximum channels on a
340 (5 modules)
340 (5 modules)
340 (5 modules)
170 (5 modules)
single time base and trigger
Memory depth
16715A, 16717A: 4/2M [2]
16740A: 2/1 M [2]
16750A: 8/4M [2]
128/64M [5]
(half/full channel)
16716A: 1M/512K [2]
16741A: 8/4 M [2]
16751A: 32/16M [2]
16742A 32/16 M [2]
16752A: 64/32M [2]
Trigger resources
Patterns: 16
Pattern: 16
Patterns: 16
At 800 Mb/s: 4 patterns or
Ranges: 15
Ranges: 15
Ranges: 15
2 ranges, 4 flags, arm in
Edge & Glitch: 2
Edge & Glitch: 2
Edge & Glitch: 2
At 200 Mb/s: same as
16750A,
Timers: (2 per module) -1
Timers: (2 per module) –1
Timers: (2 per module) -1
16751A, 16752A
Occurrence Counter: [4]
Occurrence Counter: 2
Occurrence Counter: [4]
Other speeds: refer to
Global Counters: 2
Global Counter: 2
Global Counters: 2
synchronous state analysis
Flags: 4
Flags: 4
Flags: 4
(page 98) and asynchronous
timing analysis (page 100)
Maximum trigger sequence levels
16
16
16
1.25 Gb/s: 2
800 Mb/s: 4
200 or 400 Mb/s: 16
Maximum trigger sequence speed
16715A, 16716A: 167 MHz
200 MHz
400 MHz
1.25 Gb/s
16717A: 333 MHz
Trigger sequence level branching
4-way arbitrary “IF/THEN/ELSE”
4-way arbitary
4-way arbitrary “IF/THEN/ELSE” 800 or 1.25 Gb/s: none
branching
“IF/THEN/ELSE”
branching
200 Mb/s: arbitrary
branching
“IF/THEN/ELSE” branching
400 Mb/s: dedicated next-
state branch or reset
Number of state clocks/qualifiers
4
4
4
1 (state clock only)
Setup/hold time*
2.5 ns window adjustable from
2.5 ns windows adjustable from
2.5 ns window adjustable from
1 ns window adjustable from
4.5/-2.0 ns to -2.0/4.5 ns in 100 ps
4.5/2.0 ns to -2.0/4.5 ns in 100 ps
4.5/-2.0 ns to -2.0/4.5 ns in 100 ps 2.5/-1.5 ns to -1.5/2.5 ns
increments per channel [3]
increments per channel [3]
increments per channel [3]
10 ps increments per channel
Threshold range
TTL, ECL, user-definable ±6.0 V
TTL, ECL, user-definable ±6.0 V
TTL, ECL, user-definable ±6.0 V
-3.0 V to 5.0 V adjustable in
adjustable in 10-mV increments
adjustable in 10-mV increments
adjustable in 10-mV increments
10-mV increments
* All specifications noted by an asterisk are the performance standards against which the product is tested.
[1] State speeds greater than 167 MHz (16717A) or 200 MHz (16750A, 16751A, 16752A, 16760A) require a trade-off in features.
Refer to “Supplemental Specifications and Characteristics” on page 93 for more information.
[2] Memory depth doubles in half-channel timing mode only.
[3] Minimum setup/hold time specified for a single clock, single edge acquisition. Multi-clock, multi-edge setup/hold window add 0.5 ns.
[4] There is one occurrence counter per trigger sequence level.
[5] Memory depth doubles in half-channel 1.25 Gb/s state mode only.
