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Agilent Technologies 16700 Series, Product Overview

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82

Mainframe Specifications and
Characteristics

Agilent 16700A Series Physical
Characteristics

Power

16700A

115/230 V, 48 to 66 Hz, 610 W max

16701A

115/230 V, 48 to 66 Hz, 545 W max

16702A

115/230 V, 48 to 66 Hz, 610 W max

Weight*

Max Net

Max Shipping

16700A

12.7 kg (27.0 lb)

34.2 kg (75.4

lbs)
16701A

10.4 kg (23.0 lb)

32.0 kg (70.6

lbs)
16702A

15.2 kg (32.4 lb)

36.7 kg (80.8

lbs)

* Weight of modules ordered with mainframes will add

0.9 kg (2.0 lb) per module.

Built-in LCD Display

3.5 Inch Floppy
Disk Drive

On/Off 
Power Switch

Screen Intensity Adjustment

Parallel Port

Monitor

RS-

LAN 10BaseT

SCSI-2 Single Ended

Two Slots for
Emulation
Modules

Mouse

Keyboard

Expansion Frame Cable Connector

Five Slots for
Measurement
Modules

Target Control Port

Port IN

Port OUT

Dimensions: mm (inches)

A
B
C
D
E

548.64 (21.6”)

234.2

(9.22”)

425.7 (16.76”)

Figure 6.6. Exterior dimensions for the 16700A Series mainframe.

Figure 6.4. Agilent 16702A front panel.

Figure 6.5. Back panel for Agilent models 16700A and 16702A.

556.3 (21.9”)

482.6 (19.0”)

Keypads for Alpha-Numeric Entry

1

2

LAN 10Base2

Summary of Contents for 16700 Series

Page 1: ...e and innovative hardware technologies make it difficult to meet your time to market goals The Agilent Technologies 16700 Series logic analysis systems provide the simplicity and power you need to con...

Page 2: ...Tool Sets page 39 Source Correlation page 41 Data Communications page 45 System Performance Analysis page 54 Serial Analysis page 61 Tool Development Kit page 67 Licensing Information page 73 Time Co...

Page 3: ...th automatic measurements of rise time voltage pulse width and frequency Pattern Generation Use stimulus to substitute for missing system components or to provide a stimulus response test environment...

Page 4: ...bility that makes complex device substitution a reality Supports TTL CMOS 3 3V 1 8V LVDS 3 state ECL PECL and LVPECL High Speed Bus Measurements Agilent s eye finder technology automatically adjusts t...

Page 5: ...System Software Features Post Processing Analysis Tools Rapidly consolidate large amounts of data into displays that provide insight into your system s behavior See page 38 Setup Assistant Quickly co...

Page 6: ...re you analyzing a microprocessor Do you need to probe a specific package type Select the measurement modules to meet your application needs State Timing Logic Analyzers page 17 Oscilloscopes page 29...

Page 7: ...s Dedicated knobs for horizontal and vertical scaling and scrolling Adjust the display to get just the information you need to solve your problem Mainframes Display Select a modifiable variable by tou...

Page 8: ...ement modules Built in 40x CD ROM drive makes it easy to install or update system software processor support or tool sets Option slot for an emulation module or for a multiframe module Multiframe opti...

Page 9: ...ser accounts for security or install software updates Demo Center provides simple demos of the most commonly used features Setup Assistant is a guided menu system that helps you configure the logic an...

Page 10: ...with limited space Color lets you highlight critical information so you can find it quickly Use one system to examine target operation from different perspec tives Multiple time correlated views of d...

Page 11: ...you were in a remote location Now you can Figure 2 6 Your logic analyzer is its own web site From the Home Page you can perform multiple remote functions With a Web Enabled Logic Analysis System You C...

Page 12: ...mes IntuiLink Figure 2 7 Transfer data into Microsoft Excel with just a click of the mouse Agilent IntuiLink Moves Your Data Automatically into Microsoft Excel for Advanced Offline Analysis IntuiLink...

Page 13: ...utline Package TSOP Thin Small Outline Package Package Pin Pitch distance between pin centers Immunity to Noise EMF noise is everywhere and can corrupt your data Active attenuator probing can be parti...

Page 14: ...mm or 0 65 mm QFP ICs Refer to Probing Solutions for Agilent Technologies Logic Analysis Systems publication number 5968 4632E for specific part numbers Connecting to individual test points with flyi...

Page 15: ...16518A 16760A with peak to peak amplitude as small as 250 mV E5378A 34 channel 100 pin single ended probe for 16760A 16760 68701 16760A only E5379A 17 channel 100 pin differential probe for 16760A 16...

Page 16: ...cremental cost processors and buses Only useable for the specific processor or bus May require moderate clearance around processor or bus Figure 3 10 Refer to Processor and Bus Support for Agilent Tec...

Page 17: ...ing analysis modules The things to consider are primarily state speed and memory depth Setup Hold Logic analyzers require time for the data at the inputs to become valid setup time and time to capture...

Page 18: ...yzer memory system is similar to a circular buffer When the acquisition is started the analyzer continuously gathers data samples and stores them in memory When memory becomes full it simply wraps aro...

Page 19: ...ic situation Reliable Eye finder automatically adjusts the setup and hold on every channel measurements eliminating the need for manual adjustment and ensuring the highest on high speed confidence in...

Page 20: ...cation for access to all state acquisition options Convenient color coding helps you identify the signals in the interface with the physical connection to your device under test Clocking for state mea...

Page 21: ...e flags by any module in the frame Flags allow you to set up a trigger that is dependent on activity from more than one bus in the system Specify four way arbitrary IF THEN ELSE branching Examples of...

Page 22: ...Each event can specify a combination of actions such as store sample increment counters reset timers trigger or go to another step in the sequence level Ranges provide a way to monitor program and dat...

Page 23: ...ng and available in the 16716A 400 MHz state across all channels all the time through the same 16717A 16740A 16741A connection 16742A 16750A 16751A Vary the Timing Zoom sample rate from 250 MHz to 2 G...

Page 24: ...t is required You only need to run eye finder once when the logic analyzer is set up and connected to the target Figure 4 4 The eye finder display Gray shading indicates regions where transitions are...

Page 25: ...ed Eye Finder Eye finder becomes critical when the data valid window is 2 5 ns If you re unsure where your clock edge is relative to the data valid window you can run eye finder for maximum confidence...

Page 26: ...Features Supported in Agilent State and Timing Analysis Modules Agilent Module Number 16710A 16711A 16715A 16716A 16717A 16760A 16712A 16740A 16741A 16742A 16750A 16751A 16752A Eye finder Visitrigger...

Page 27: ...ps resolu tion Small amplitude signals Many high speed designs use small signal amplitudes to limit slew rates and reduce power Agilent s 16760A can make reliable measurements on signals as small as...

Page 28: ...cursor Eye limit The eye limit tool is a single point cursor that can be positioned manu ally The readout indicates the inner eye limits detected at the time and voltage coordinates of the cursor His...

Page 29: ...red to support all 34 channels on a 16760A Requires a kit of mating connectors and shrouds see the next table to connect to target system E5380A 012 38 pin single ended probe compatible Maximum state...

Page 30: ...nother That s why the abil ity to view your prototype s behavior from all angles simultaneously from software execution to analog signals is essential for quickly gaining insight into problems For exa...

Page 31: ...nd Voltage Margin Measurements Four independent voltage markers and two local time markers are avail able to quickly set up measurements of voltage and timing margins The global time markers of the 16...

Page 32: ...s MAX 16534A 2 GSa s OSCILLOSCOPE CHAN 1 CHAN 2 IN OUT ECL EXT TRIG SN US35021924 16534A MADE IN THE USA PROBE POWER AC DC CAL Channel 1 input Figure 4 7 Connector panel of the 16534A oscilloscope mod...

Page 33: ...l half channel 48 24 Channels Memory depth full half channels 8 16 MVectors Maximum vector width 240 120 Bits 5 module system full half channel Logic levels supported TTL 3 state TTL 3 3V 1 8V 3 state...

Page 34: ...to convert VCD files into PGB files directly offering you an integrated solution that saves you time Synchronized Clock Output You can output data synchronized to either an internal or external clock...

Page 35: ...In this example vector output halts until the WAIT UNTIL condition is satisfied Figure 4 9 To fill the 16720A pattern generator s 8 MVector deep memory 16 MVector in half channel mode with data the st...

Page 36: ...cros and loops also are not supported so the vectors need to be fully expanded in the ASCII file Many design tools will generate ASCII files and output the vectors in this linear sequence Data must be...

Page 37: ...bus architectures such as PCI AGP USB VXI SCSI and many others Flexible physical probing schemes give quick and reliable connections to almost any device on your prototype On Chip Emulation Tools Make...

Page 38: ...or memory access or to reinitialize memory areas Multiple breakpoint configuration hardware software and processor internal breakpoint registers Code download to the target Command scripts to reproduc...

Page 39: ...ting and clicking on a line of source code Debug your parallel data communication buses Data Communications B4640B Page 44 Display logic analyzer trace information at a protocol level Tool Set Powerfu...

Page 40: ...emo in the password field for the product you want to evaluate Free Tool Set Evaluation To see which tool sets best fit your needs Agilent Technologies offers a free 21 day trial period that lets you...

Page 41: ...system failure hardware or software Are timing anomalies found by the hardware engineer the cause of software problems Is the software engineer working on the same problem as the hard ware engineer Wh...

Page 42: ...function or line number to halt processor execution with an integrated emulation module when the trace event occurs to use text search to quickly navigate through hundreds of symbols To recall previo...

Page 43: ...or without viewing calls to subroutines or interrupts by using the analyzer s filtering capabilities to focus on a specific part of the executed software scroll or step through the time correlated sou...

Page 44: ...ROM to RAM during a boot up sequence High level language tools that pro duce the following file formats are supported Agilent HP MRI IEEE696 ELF DWARF ELF Stabs TI_COFF COFF Stabs Intel OMF86 Intel OM...

Page 45: ...in a raw hex format Filters are included to allow many different views of the data Protocol layers can be collapsed or expanded to create a custom view of the data acquired in the logic analyzer With...

Page 46: ...Data Valid allow the logic analyzer to sample only on events of interest instead of all cycles With access to the Start of Cell or Start of Packet bit on the data bus the analyzer starts looking at th...

Page 47: ...ng the protocol setup information via the logic analyzer interface or a text file Custom protocol definitions are used in both the trigger definition and packet display Trigger Macro All custom define...

Page 48: ...t name num ber of bits and format for trigger and display Define any sym bols for both trigger and display of packets Edit or create a protocol using a text file Start with stan dard protocol definiti...

Page 49: ...tead of setting up trig ger sequencer Specify what action to perform once a packet is found Specify protocol layer to trigger on Use any defined protocol fields as a trigger such as source address des...

Page 50: ...cessing and Analysis Tool Sets Data Communications Use the bus editor feature to specify what protocol runs on your bus This is helpful when probing more than one bus with a single state timing module...

Page 51: ...Data Communications Protocol Filters and Viewing Preferences Filter captured data to only view key data for measurement Choose to view payload data with header information Select which protocol layer...

Page 52: ...Analysis Tool Sets Data Communications Display of protocol levels Protocol view of data acquired in logic analyzer Time tags for system level correlation of other data buses memory interfaces micropro...

Page 53: ...lobal markers measure time intervals between packets on separate parallel interfaces or timing between the data path and a microprocessor Collapsed view of protocol infor mation using pref erences Raw...

Page 54: ...uate Is the cache size adequate Analog Timing and Bus Measurements What is the setup hold time of this signal or group of signals Is the distribution of voltages for this analog signal acceptable Is t...

Page 55: ...specific Views the frequency of First step of analysis or that are candidates for routine s execution times events over time optimization process to duration measurements and verifies signal timing id...

Page 56: ...isition Object File Format Object file formats are identical for SPA and the source correlation tool sets See page 43 Compatibility Off Line Analysis and All measurements can be saved using the file o...

Page 57: ...nd zoom functions Pinpoint regions of high memory activity to determine which routines or operations are responsible for throughput bottlenecks Measure memory coverage or stack usage by observing whet...

Page 58: ...ion utility The util ity automatically configures the tool for the selected function and variable names from large symbol files created by complex software projects To help simplify your display delet...

Page 59: ...deviation and mean help you document system behav ior Use accumulate mode to analyze the behavior of your system over a long period of time Because time interval measurements often depend upon hardwa...

Page 60: ...ous service requests the system can exhibit random defects while leaving no clues as to their cause In this situ ation you need a tool that can meas ure and display interrupt loading Use Comments to...

Page 61: ...How does the serial bus activity correlate to the target system processor What is causing the data corrup tion in the target system Product Description The Agilent Technologies B460lB seri al analysis...

Page 62: ...s with clocking embedded within the serial bit stream accept the default output label Parallel or modify the label name for easy recognition set the output parallel word width up to 32 bits select the...

Page 63: ...your framing and data block selections remove stuffed 0s or 0 1s from the trace before other serial analysis functions are performed Some proto cols use bit stuffing to maintain clock synchronization...

Page 64: ...are used to resynchronize the sampling To Acquire a Serial Bit Stream without an External Clock Reference set the sample period of your timing analyzer to take four or more samples for each serial bit...

Page 65: ...to parallel con version to the start of the frame pattern for your spe cific bus convert the data block into parallel words in this case 8 bit words find the Nth occurrence of specific frames or data...

Page 66: ...ved using the file out tool Data can be recalled at any time for later analysis using any analysis or display tool Serial measurement data can be exported to your host computer as ASCII files Serial M...

Page 67: ...uage programming background is highly recommended A tutorial extensive examples and a rich library of functions are provided that help you easily access analyzer data and the tool s interface The cust...

Page 68: ...utomobile Embedded in the data is information about the engine and transmission When MODE 0 DATA represents engine information including RPM fuel level fuel to air ratio and mani fold pressure When MO...

Page 69: ...code flow after the trace was taken The code was reconstructed by using the branch trace messages and information in the SRecord file creat Original Trace Output of Custom Tool Parameter Window of Cus...

Page 70: ...ent labels The labels can even come from different analyzers At left are the parameter window and message display created by the custom tool in this example Parameters allow the user to control differ...

Page 71: ...on to compile the code displayed in the Source Code tab Load a file created on another system or create your code here using the Source Code editor Compilation status is shown at the bottom of the too...

Page 72: ...ations such as creating ASCII or binary files reading from these files writing or appending to these files and IEEE 764 floating point operations Provided Functions Agilent Technologies provides a ric...

Page 73: ...ck Mode Tool set licenses are shipped or first installed as nodelocked applications Nodelocked means that use of the tool set license is only allowed on the single node 16700 Series analyzer on which...

Page 74: ...eration of A D and D A converters Verifying correct logical and tem poral relationships between the analog and digital portions of a design Agilent s E5850A time correlation fixture works in conjuncti...

Page 75: ...256 MB total time of frame purchase Supported Monitor Resolutions Standard 640 x 480 through 1280 x 1024 The 16702B has a built in 800 x 600 12 1 26 2mm diagonal monitor Option 003 Must be ordered at...

Page 76: ...or higher IntuiLink Support Installation of PC Application Software Directly from instrument web page MS Excel Excel 97 Version 7 0 or later Excel limits maximum trace depth to 64K per sheet Availabl...

Page 77: ...122 F Disk Media 10 C to 40 C 50 F to 104 F Probes Cables O C to 65 C 32 F to 149 F Altitude To 3000m 10 000 ft Humidity 8 to 80 relative humidity at 40 C 104 F Printing Printer Interface Parallel int...

Page 78: ...iguration and captured data Exports data Executes a compare Modifies the trigger setup or trigger value for the next acquisition Accesses the oscilloscope s automatic measurements Physical Connection...

Page 79: ...Generator Load Save Configuration and Data Load ASCII file vectors or PGB pattern generator binary files 16720A only Modify Vector Set Query Clock Frequency Set Query Clock Out Delay Insert New Vector...

Page 80: ...with LabVIEW 5 1 or higher This library contains five LabVIEW samples that provide a starting point for creating your own LabVIEW programs Load Run Save loads a configuration runs a measurement then...

Page 81: ...add 0 9 kg 2 0 lb per module 12 1 Built in LCD Display with Touch Screen 3 5 Inch Floppy Disk Drive On Off Power Switch Touch Screen On Off Parallel Port Monitor RS LAN 10BaseT 100BaseT X SCSI 2 Singl...

Page 82: ...kg 2 0 lb per module Built in LCD Display 3 5 Inch Floppy Disk Drive On Off Power Switch Screen Intensity Adjustment Parallel Port Monitor RS LAN 10BaseT SCSI 2 Single Ended Two Slots for Emulation Mo...

Page 83: ...ND 16 SIGNAL GND 18 SIGNAL GND 20 SIGNAL GND 22 SIGNAL GND 24 SIGNAL GND 26 SIGNAL GND 28 SIGNAL GND 30 SIGNAL GND 32 SIGNAL GND 34 SIGNAL GND 36 SIGNAL GND 38 SIGNAL GND 40 POWER GND 5V 1 CLK1 3 CLK2...

Page 84: ...of the probe cable are designed to perform two functions The first is to reduce the number of pins required for the header on the target board from 40 pins to 20 pins This process reduces the board a...

Page 85: ...s 16 16 16 1 25 Gb s 2 800 Mb s 4 200 or 400 Mb s 16 Maximum trigger sequence speed 16715A 16716A 167 MHz 200 MHz 400 MHz 1 25 Gb s 16717A 333 MHz Trigger sequence level branching 4 way arbitrary IF T...

Page 86: ...Maximum trigger sequence speed 125 MHz Trigger sequence level branching Dedicated next state or single arbitrary branching Number of state clocks qualifiers 6 Setup hold time 4 0 ns window adjustable...

Page 87: ...um master to master clock time 16710A 16711A 16712A 10 ns Minimum master to slave clock time 0 0 ns Minimum slave to master clock time 4 0 ns Context store block sizes 16 32 64 states 16710A 11A 12A o...

Page 88: ...range 400 ns to 500 seconds Timer resolution 16 ns or 0 1 whichever is greater Timer accuracy 32 ns or 0 1 whichever is greater Operating Environment Temperature Agilent 16700 Series mainframes Instru...

Page 89: ...ng Zoom Agilent 16716A 16717A 16740A 16741A 16742A 16750A 16751A 16752A only Timing analysis sample rate 2 GHz 1 GHz 500 MHz 250 MHz Sample period accuracy 50 ps Channel to channel skew 1 0 ns Time in...

Page 90: ...ingle edge 2 0 4 5 ns in 100 ps increments per channel 2 0 4 5 ns in 100 ps increments per channel Setup hold time 1 3 0 ns window adjustable from 5 0 2 0 ns to 3 0 ns window adjustable from 5 0 2 0 n...

Page 91: ...rary Boolean combinations Arbitrary Boolean combinations Trigger actions Goto Goto Trigger and fill memory Trigger and fill memory Trigger and goto Trigger and goto Store don t store sample Store don...

Page 92: ...0 ps increments per channel Setup hold time 1 3 0 ns window adjustable from 5 0 2 0 ns to 3 0 ns window adjustable from 5 0 2 0 ns to single clock multi edge 1 5 4 5 ns in 100 ps increments per channe...

Page 93: ...iming Mode 16715A 16716A 16717A 16740A 16741A 16742A 16750A 16751A 16752A Timing analysis sample rate 667 333 MHz 800 400 MHz half full channel Channel count 68 per module 68 per module Maximum channe...

Page 94: ...Flags 4 Flags Trigger resource conditions Arbitrary Boolean combinations Arbitrary Boolean combinations Trigger actions Goto Goto Trigger and fill memory Trigger and fill memory Trigger and goto Trigg...

Page 95: ...r interface Maximum nondestructive 40 Vdc 40 Vdc 40 Vdc 40 Vdc input voltage Maximum input slew rate 5 V ns 5 V ns 5 V ns 5 V ns Clock input Differential Differential Single ended Differential Number...

Page 96: ...ested 1 The analyzer can be configured to sample on the rising edge the falling edge or both edges of the clock If both edges are used with a single ended clock input take care to set the clock thresh...

Page 97: ...80 5 modules 170 5 modules 153 5 modules 170 5 modules single time base and trigger Maximum memory depth 128M samples 128M samples 64M samples 32M samples 32M samples Time tag resolution 4 ns 2 4 ns 2...

Page 98: ...A N A 10 ns 0 01 of value Timer reset latency N A N A N A N A 65 ns Data in to BNC port out 150 ns 150 ns 150 ns 150 ns 150 ns latency Flag set reset to evaluation N A N A N A N A 110 ns latency 1 In...

Page 99: ...ule 1 2 Global counters 2 Global counters 1 Occurrence counter per sequence level 1 Occurrence counter per sequence level 4 Flags Arm In 4 Flags Arm In Trigger resource conditions Arbitrary Boolean co...

Page 100: ...s between any two channels 1 E5378A E5379A and E5382A probes only Qualified eye scan mode In the qualified eye scan mode a single qualifier input defines what clock cycles are to be acquired and what...

Page 101: ...cations apply only within 10 C of the temperature at which the most recent calibration was performed Specifications apply only after operational accuracy calibration is performed in the frame in which...

Page 102: ...libration temperature dc offset range Vertical sensitivity Offset range 16 mV full scale to 400 mV full scale 2 V 400 mV full scale to 2 0 V full scale 10 V 2 0 V full scale to 10 V full scale 50 V 10...

Page 103: ...notes 1 5 x full scale from center of screen Trigger modes Immediate Triggers immediately after arming condition is met Edge Triggers on rising or falling edge on channel 1 or channel 2 Pattern Trigge...

Page 104: ...o define a pattern 3 Maximum number of modules in a system 5 Maximum width of a vector in a 5 module system 240 bits Maximum width of a label 32 bits Maximum number of labels 126 Maximum number of vec...

Page 105: ...l 2 ns worst case 4 ns Recommended lead set Agilent 10474A Agilent 10462A 3 State TTL CMOS Data Pod Output type 74ACT11244 with 100 series 10H125 on non 3 state channel 7 2 3 state enable negative tru...

Page 106: ...a non 3 state signal By looping this output back into the 3 state enable line the channel can be used as a 3 state enable Agilent 10465A ECL Data Pod unterminated Output type 10H115 no termination Ma...

Page 107: ...ny channel within a single or multiple module system 2 Channel 7 on the 3 state pods has been brought out in parallel as a non 3 state signal By looping this output back into the 3 state enable line t...

Page 108: ...4 3 state enable negative true 38 K to GND enabled on no connect Maximum clock 300 MHz Skew 1 typical 1 5 ns worst case 2 ns Recommended lead set Agilent 10498A Agilent 10483A 3 State 3 3 Volt Data Po...

Page 109: ...ntial signal from a type 10E156 or 10E154 driver These are usable when received by a differential receiver preferably with a 100 termination across the lines These signals should not be used single en...

Page 110: ...1 K to 5 2V differential signal from a type 10E164 driver These are usable when received by a differential receiver preferably with a 100 termination across the lines These signals should not be used...

Page 111: ...1 clk period Recommended lead set Agilent 10474A 10H116 5 2 V VBB 50 k CLKin 10H116 5 2 V 330 47 CLKout Pattern Generation Modules Specifications and Characteristics Clock Pod Characteristics 10460A...

Page 112: ...to recognition approximately 15 ns 1 clk period Recommended lead set Agilent 10498A 10470A 3 3 volt LVPECL Clock Pod Clock output type 100LVEL90 3 3V with 215 ohm pulldown to ground and 42 ohm in ser...

Page 113: ...ttern in to recognition approximately 15 ns 1 clk period Recommended lead set Agilent 10498A 10475A 1 8 volt Clock Pod Clock output type 74AVC16244 Clock output rate 200 MHz maximum Clock out delay ap...

Page 114: ...tion approximately 15 ns 1 clk period Recommended lead set Agilent 10498A CLKout 74AVC16244 74AVC16244 WAIT CLKin E8140A LVDS Clock Pod Clock output type 65LVDS179 LVDS and 10H125 TTL Clock output rat...

Page 115: ...rms and Conditions This offer is void where prohibit ed This offer applies to end user cus tomers only Rental companies and equipment brokers are exclud ed This offer is applicable to the return of fe...

Page 116: ...B or 16702A B 1184A Testmobile 4 wheeled equipment cart specifically designed Drawer keyboard tray mouse tray strap for to carry the 16700 Series logic analyzer stabilizing monitor expansion frame an...

Page 117: ...s 772 2 30 4 482 6 19 0 254 10 0 243 8 9 6 774 7 30 5 866 1 34 1 116 8 4 6 594 4 23 4 190 5 7 5 469 9 18 5 652 8 25 7 584 2 23 0 E5850A Logic Analyzer Infiniium Oscilloscope Correlation Time Fixture P...

Page 118: ...th 16711A 100 MHz State 500 MHz Timing 32 K memory depth 16712A 100 MHz State 500 MHz Timing 128 K memory depth 16715A 167 MHz State 667 MHz Timing 2 4 M memory depth 16716A 167 MHz State 667 MHz Timi...

Page 119: ...in 20 Channel 16720A 300 MV s 180 MHz in 48 Channel 16 MV memory 300 MHz in 24 Channel 8 MV memory Emulation E5901A Emulation Module Products E5901B Emulation Module Products Discontinued products Opt...

Page 120: ...c Probing Solutions Package Type IC Leg Spacing Probe Model Number 240 pin PQFP CQFP 0 5 mm E5363A Probe E5371A 1 4 flexible cable 208 pin PQFP CQFP 0 5 mm E5374A Probe E5371A 1 4 flexible cable 176 p...

Page 121: ...1 2pF oscilloscope probe Options for Agilent 16720A Pattern Generator Modules Agilent Option Option Description 011 TTL clock pod and 6 lead set 10460A and 10498A 013 3 state TTL CMOS data pod and 6...

Page 122: ...d 10465A ECL data pod unterminated 10466A 3 state TTL 3 3V data pod 10468A 5 volt PECL clock pod 10469A 5 volt PECL data pod 10470A 3 3 volt LVPECL clock pod 10471A 3 3 volt LVPECL data pod 10472A 2 5...

Page 123: ...alysis probes for various www corelis com microprocessors and buses Diagonal Manufacturing test suite www diagonal com software Emulation Technologies ET Probing www emulation com Europe Technologies...

Page 124: ...rola IBM Power PC 740 750 Microprocessors Agilent E2487C Analysis Probe Agilent E2492B C E Product Overview 5968 2421E Probe Adapter for Intel Celeron Pentium II III and Pentium II III Xeon Processors...

Page 125: ...ct management and other professional engineering services Experienced Agilent engineers and technicians worldwide can help you maximize your productivity optimize the return on investment of your Agil...

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