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SOM-5993 User Manual

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Figure 3.7 Serial Port 1 Configuration ....................................... 28

Figure 3.8 Serial Port 2 Configuration ....................................... 29

Figure 3.9 Hardware Monitor..................................................... 29

3.4.4 Serial Port Console Redirection.................................................. 30

Figure 3.10Serial Port Console Redirection ............................... 30

Figure 3.11Console Redirection Settings ................................... 31

Figure 3.12Console Redirection Settings ................................... 32

3.4.5 PCI Subsystem Settings............................................................. 33

Figure 3.13PCI Subsystem Settings........................................... 33

Figure 3.14PCI Express Settings ............................................... 34

Figure 3.15PCI Express GEN 2 Settings.................................... 35

3.4.6 USB Configuration...................................................................... 36

Figure 3.16USB Configuration.................................................... 36

3.4.7 Network Stack Configuration ...................................................... 37

Figure 3.17Network Stack Configurations.................................. 37

3.4.8 NVMe Configuration ................................................................... 37

Figure 3.18NVMe Configuration................................................. 37

3.5

Chipset.................................................................................................... 38

Figure 3.19Chipset ..................................................................... 38

3.5.1 Socket Configuration .................................................................. 39

Figure 3.20Socket Configuration ................................................ 39

Figure 3.21Processor Configuration........................................... 40

Figure 3.22Processor Configuration........................................... 40

Figure 3.23Processor Configuration........................................... 41

Figure 3.24 Per-Socket Configuration ........................................ 42

Figure 3.25CPU Socket 0 Configuration .................................... 43

Figure 3.26PSMI Configuration .................................................. 44

Figure 3.27Socket 0 Configuration ............................................. 45

Figure 3.28IIO Configuration ...................................................... 46

Figure 3.29Socket0 Configuration.............................................. 47

Figure 3.30TraceHub Configuration Menu ................................. 48

Figure 3.31R-Link ....................................................................... 48

Figure 3.32R-Link ....................................................................... 49

Figure 3.33Port 1A ..................................................................... 50

Figure 3.34Port 1A ..................................................................... 51

Figure 3.35Advanced Power Management Configuration.......... 52

Figure 3.36CPU P State Configuration....................................... 53

Figure 3.37Perf P-Limit............................................................... 54

Figure 3.38CPU C State Configuration ...................................... 55

Figure 3.39Package C State Control.......................................... 56

Figure 3.40Latency Tolerance Requirement (LTR).................... 57

Figure 3.41PkgC SA PS Criteria Power Management Control... 58

Figure 3.42CPU0 PKGC_SA_PS_CRITERIA ............................ 59

Figure 3.43PKGc Interrupt Response Time ............................... 60

Figure 3.44Memory Topology..................................................... 61

3.5.2 Platform Configuration................................................................ 62

Figure 3.45Platform Configuration.............................................. 62

Figure 3.46PCH-IO Configuration .............................................. 63

Figure 3.47PCI Express Configuration ....................................... 64

Figure 3.48PCI Express Root Port 1 .......................................... 65

Figure 3.49PCI Express Root Port 2 .......................................... 66

Figure 3.50PCI Express Root Port 3 .......................................... 67

Figure 3.51PCI Express Root Port 4 .......................................... 68

Figure 3.52PCI Express Root Port 5 .......................................... 69

Figure 3.53PCI Express Root Port 6 .......................................... 70

Figure 3.54PCI Express Root Port 7 .......................................... 71

Figure 3.55PCI Express Root Port 8 .......................................... 72

Figure 3.56PCI Express Root Port 9 .......................................... 73

Figure 3.57PCI Express Root Port 10 ........................................ 74

Figure 3.58PCI Express Root Port 11 ........................................ 75

Summary of Contents for SOM-5993

Page 1: ...User Manual SOM 5993 CPU Computer on Module ...

Page 2: ...no liability under the terms of this warranty as a consequence of such events Because of Advantech s high quality control standards and rigorous testing most customers never need to use our repair service If an Advantech product is defective it will be repaired or replaced free of charge during the warranty period For out of warranty repairs customers will be billed according to the cost of replac...

Page 3: ...ause harmful interference to radio or television reception which can be determined by turning the equipment off and on the user is encouraged to try to correct the interference by one or more of the following measures Reorient or relocate the receiving antenna Increase the separation between the equipment and receiver Connect the equipment into an outlet on a circuit different from that to which t...

Page 4: ...information Part No CPU Cores Freq CPU TDP LLC DDR4 SODIMM Giga LAN 10G Base KR PEG X16 PEG X8 PEG X1 USB 2 0 USB 3 0 SATA III LPC Power Thermal solution Operating Temp SOM 5993D10 U0A1 D 1746TE R 10 2 0G 67W 15MB ECC non ECC 1 4 1 1 4 4 4 2 Yes AT ATX Active 0 60 C SOM 5993D8 U2A1 D 1735TR 8 2 2G 59W 15MB ECC non ECC 1 4 1 1 4 4 4 2 Yes AT ATX Active 0 60 C SOM 5993D8 S9A1 D 1732TE 8 1 9G 25W 15M...

Page 5: ...s before manual handling Do not touch any components on the CPU card or other cards while the PC is powered on Disconnect the power before making any configuration changes A sudden rush of power after connecting a jumper or installing a card may damage sensitive electronic components Part No Description Quantity SOM 5993 module 1 x 1970005371T001 Standard Heatspreader 1 x Part No Description SOM D...

Page 6: ...ur liquid into an opening This may cause fire or electrical shock 13 Never open the equipment For safety reasons the equipment should be opened only by qualified service personnel 14 If any of the following occurs have the equipment checked by service person nel The power cord or plug is damaged Liquid has penetrated the equipment The equipment has been exposed to moisture The equipment is malfunc...

Page 7: ... Identification Front 16 Figure 2 2 Board Chips Identification Back 16 2 1 1 Connector List 17 Table 2 1 FAN1 Fan 17 2 2 Mechanical Diagram 17 Figure 2 3 Board Mechanical Diagram Front 17 Figure 2 4 Board Mechanical Diagram Back 18 Figure 2 5 Board Mechanical Diagram Side 18 2 3 Assembly Drawing 19 Figure 2 6 Assembly Diagram 19 2 4 Assembly Drawing 20 Figure 2 7 Main Chip Height and Tolerance 20 ...

Page 8: ...ocket 0 Configuration 45 Figure 3 28IIO Configuration 46 Figure 3 29Socket0 Configuration 47 Figure 3 30TraceHub Configuration Menu 48 Figure 3 31R Link 48 Figure 3 32R Link 49 Figure 3 33Port 1A 50 Figure 3 34Port 1A 51 Figure 3 35Advanced Power Management Configuration 52 Figure 3 36CPU P State Configuration 53 Figure 3 37Perf P Limit 54 Figure 3 38CPU C State Configuration 55 Figure 3 39Package...

Page 9: ...Enabling 89 Figure 3 76PCIe Error Enabling 91 Figure 3 77PCIe Error Enabling 91 Figure 3 78Error Control Setting 92 3 6 Server Mgmt 93 Figure 3 79Server Mgmt 93 3 7 Security 94 Figure 3 80Security 94 3 7 1 Secure Boot 95 Figure 3 81Secure Boot 95 3 8 Boot 96 Figure 3 82Boot 96 3 9 Save and Exit 97 Figure 3 83Save and Exit 97 Chapter 4 S W Introduction Installation 99 4 1 S W Introduction 100 4 2 D...

Page 10: ...SOM 5993 User Manual x Table D 2 DMA Channel Assignments 115 D 3 Interrupt Assignments 116 Table D 3 Interrupt Assignments 116 D 4 1st MB Memory Map 116 Table D 4 1st MB Memory Map 116 ...

Page 11: ...Chapter 1 1 General Information This chapter details background information on the SOM 5993 CPU Computer on Module Sections include Introduction Functional Block Diagram Product Specifications ...

Page 12: ... GbE Gigabit Ethernet GPIO General purpose input output HDA Intel High Definition Audio HD Audio refers to the specification released by Intel in 2004 for delivering high definition audio that is capable of playing back more channels at higher quality than AC 97 I2C Inter Integrated Circuit 2 wire clock and data signaling scheme allowing communication between integrated circuit primarily used to r...

Page 13: ... features ruggedized SODIMM for improved vibration and shock resistance and supports TPM2 0 onboard chips for cyber security Likewise its wide power input and temperature support 9 12V 40 85 C is ideal for diverse applications In terms of software SOM 5993 supports WISE DeviceOn for remote hardware moni toring and over the air software updates SOM 5993 features 4 x screw holes near the CPU positio...

Page 14: ...SOM 5993 User Manual 4 1 2 Functional Block Diagram ...

Page 15: ...P on LVDS CH A Pins N A N A VGA Port N A N A Serial Ports 1 2 0 2 2 CAN Interfaces on SER1 0 1 1 Optional SATA SAS Ports 0 2 2 HDA Digital Interface N A N A USB 2 0 Ports Host 4 4 4 USB0 Client USB 2 0 0 1 0 1Gb LAN Port 0 1 1 1 LPC Bus eSPI 1 1 1 LPC SPI 1 2 1 Row System Management R3 0 Type 7 SOM 5993 A B SDIO Muxed on GPIO 0 1 0 General Purpose I O 8 8 8 SMBus 1 1 1 I2C 1 1 1 Optional Watchdog ...

Page 16: ... I O R3 0 Type 7 SOM 5993 C D PCI Express Lanes 16 31 PEG 0 16 16 PCI Express Lanes 6 7 0 2 2 10G LAN Port 0 3 0 4 4 Digital Display Interfaces 1 3 N A N A USB 3 0 Ports 0 4 4 Rapid Shutdown 0 1 1 Row Power R3 0 Type 7 SOM 5993 C D VCC_12V Contacts 12 12 12 CPU Std Freq Max Turbo Freq Core Thread LLC Cache TDP W Xeon D 1746TER 2 0 GHz 3 1 GHz 10 20 15MB 67W Xeon D 1735TR 2 2 GHz 3 4 GHz 8 16 15MB ...

Page 17: ...nterface PCIe x16 31 16 Intel Xeon Processor D natively integrates 1 x PCIe x16 interface with support for up to 4 x devices at up to Gen4 speeds 8 GHz SOM 5993 supports 1x PCIe x16 and is configurable to 4 x4 2 x4 and 1 x8 or 1 x8 and 2 x4 or 2 x8 Note Installing memory modules in pairs on SOM 5993 requires filling the lowest numbered slots first For example the SOM 5993 has two slots each for ch...

Page 18: ...x2 2 x2 and 1 x4 or 2 x4 1 3 7 LPC This solution supports Low Pin Count LPC 1 1 specifications without DMA or bus mastering This allows it to connect super I O embedded controllers or TPM LPC clock is 25MHz 1 3 8 Serial Bus 1 3 8 1 SMBus Support SMBus 2 0 specifications with alert pins 1 3 8 2 I2C Bus Supports I2C bus 8 bit and 10 bit address modes at both 100KHz and 400KHz Type 7 Row A B Row C D ...

Page 19: ...U3 for USB 3 0 to save power 1 3 9 4 USB 3 0 1 3 9 5 USB 2 0 1 3 9 6 SPI Bus Supports BIOS flash only SPI clock can be 50MHz 33MHz or 20MHz capacity up to 16MB 1 3 9 7 GPIO 8 x programmable general purpose Input or output GPIO 1 3 9 8 Watchdog Supports multi level watchdog time out output Provides 1 65535 level from 100ms to 109 22 minutes interval 1 3 9 9 Serial port 2 x ports 2 wire serial port ...

Page 20: ...is cleared we strongly suggest going to the BIOS setup menu and loading default settings following the first boot up Purpose The standard module has no jumper at SCN1 Therefore the BIOS settings are maintained without a RTC coin battery If you need to restore the BIOS default settings please follow the steps below BIOS_DIS0 BIOS_DIS 1 Boot up destination function Open Open Boot from Module s SPI B...

Page 21: ...ations 1 3 10 4 Wake Event Diverse wake up events support different scenarios Wake on LAN WOL Wake to S0 from S4 S5 USB Wake Wake to S0 from S4 PCIe Device Wake depends on user inquiry and may need customized BIOS LPC Wake depends on user inquiry and may need customized BIOS 1 3 10 5 Advantech S5 ECO Mode Deep Sleep Mode Advantech iManager provides additional features that allow systems to enter a...

Page 22: ...s and Microsoft Windows embedded technology We enable Windows Embedded software products on Advantech platforms to more effectively support the embedded computing community Customers are freed from the hassle of dealing with multiple vendors hardware suppliers system integrators embedded OS distributors for projects Our goal is to make Windows Embedded software solu tions easily and widely availab...

Page 23: ... or benchmark data to compare with other modules please refer to Advantech COM Performance Power Consumption Table 1 3 17 Pin Description Advantech provides useful checklists for schematic design and layout routing The schematic checklist will specify details about the electrical properties of each pin and how to connect it in different user scenarios The layout checklist will specify the lay out ...

Page 24: ...SOM 5993 User Manual 14 ...

Page 25: ...Chapter 2 2 Mechanical Information This chapter details mechanical information on the SOM 5993 CPU Computer on Module Sections include Board Information Mechanical Diagram Assembly Diagram ...

Page 26: ...s on SOM 5993 Computer on Module Please be aware of these positions while designing customer carrier boards to avoid mechanical problems Use thermal solution contacts for improved thermal perfor mance Figure 2 1 Board Chips Identification Front Figure 2 2 Board Chips Identification Back ...

Page 27: ...ram For more information on 2D 3D models please visit the Advantech COM support ser vice website at http com advantech com Figure 2 3 Board Mechanical Diagram Front Table 2 1 FAN1 Fan FAN1 Fan Description Wafer 2 0 mm 3P 90D M DIP 2001 WR 03 LF W Lock Pin Pin Name 1 Fan Tacho Input 2 Fan Out 3 GND ...

Page 28: ...SOM 5993 User Manual 18 Figure 2 4 Board Mechanical Diagram Back Figure 2 5 Board Mechanical Diagram Side ...

Page 29: ...l Information 2 3 Assembly Diagram These figures demonstrate the assembly order of the thermal module COM module and carrier board Figure 2 6 Assembly Diagram There are 4 x reserved screw holes for SOM 5993 to be pre assembled with heat spreader ...

Page 30: ...ram Consider the CPU and chip height tolerance when designing your thermal solution Figure 2 7 Main Chip Height and Tolerance Package height 4 378 mm TOL 0 242 mm Post SMT stackup height based on limited data from Intel reference board design ...

Page 31: ...Chapter 3 3 AMI BIOS This chapter details BIOS setup information for the SOM 5993 CPU computer on module Sections include Introduction Entering Setup Hot Operation Key Exit BIOS Setup Utility ...

Page 32: ...S settings and control various system features This chapter describes the basic navigation of the BIOS Setup Utility Figure 3 1 Setup Program Initial Screen AMI s BIOS ROM has a built in Setup program that allows users to modify the basic system configuration This information is stored in flash ROM so it retains the Setup information when the power is turned off ...

Page 33: ...een has two main frames The left frame displays all the options that can be configured Grayed out options cannot be configured options in blue can The right frame displays the key legend Above the key legend is an area reserved for a text message When an option is selected in the left frame it is highlighted in white Often a text message will accom pany it System time System date Use this option t...

Page 34: ...e left frame of the screen such as CPU Configuration to go to the sub menu for that item Users can display an Advanced BIOS Setup option by highlighting it using the Arrow keys All Advanced BIOS Setup options are described in this section The Advanced BIOS Setup screens are shown below The sub menus are described on the following pages Figure 3 3 Advanced BIOS Features Setup Screen ...

Page 35: ...IOS 3 4 1 Trusted Computing Figure 3 4 Trusted Computing Security Device Support SHA A PCR Bank SHA256 PCR Bank Pending operation Platform Hierarchy Endorsement Hierarchy TPM 2 0 UEFI Spec Version Physical Presence Spec Version Device Select ...

Page 36: ...SOM 5993 User Manual 26 3 4 2 ACPI Settings Figure 3 5 ACPI Settings Enable ACPI Auto Configuration ...

Page 37: ...er 3 AMI BIOS 3 4 3 Embedded Controller Figure 3 6 Embedded Controller CPU Shutdown Temperature Smart Fan COM Module Smart Fan Carrier Board Power Saving Mode Serial Port 1 Configuration Serial Port 2 Configuration Hardware Monitor ...

Page 38: ...SOM 5993 User Manual 28 3 4 3 1 Serial Port 1 Configuration Figure 3 7 Serial Port 1 Configuration Serial Port Change Settings ...

Page 39: ...29 SOM 5993 User Manual Chapter 3 AMI BIOS 3 4 3 2 Serial Port 2 Configuration Figure 3 8 Serial Port 2 Configuration Serial Port Change Settings 3 4 3 3 Hardware Monitor Figure 3 9 Hardware Monitor ...

Page 40: ... 5993 User Manual 30 3 4 4 Serial Port Console Redirection Figure 3 10 Serial Port Console Redirection Console Redirection Console Redirection Settings Console Redirection EMS Console Redirection Settings ...

Page 41: ...r 3 AMI BIOS 3 4 4 1 Console Redirection Settings Figure 3 11 Console Redirection Settings Terminal Type Bits per second Data Bits Parity Stop Bits Flow Control VT UTF8 Combo Key Support Recorder Mode Resolution 100x31 Putty KeyPad ...

Page 42: ...SOM 5993 User Manual 32 3 4 4 2 Console Redirection Settings Figure 3 12 Console Redirection Settings Out Of Band Mgmt Port Terminal Type EMS Bits per second EMS Flow Control EMS ...

Page 43: ... 5 PCI Subsystem Settings Figure 3 13 PCI Subsystem Settings PCI Latency Timer PCI X Latency Timer VGA Palette Snoop PERR Generation SERR Generation Above 4G Decoding SR IOV Support BME DMA Mitigation PCI Express Settings PCI Express GEN 2 Settings ...

Page 44: ... 4 5 1 PCI Express Settings Figure 3 14 PCI Express Settings Relaxed Ordering Extended Tag No Snoop Maximum Payload Maximum Read Request ASPM Support Extended Synch Link Training Retry Link Training Timeout uS Unpopulated Links ...

Page 45: ... 15 PCI Express GEN 2 Settings Complete Timeout ARI Forwarding AtomicOp Requester Enable AtomicOp Egress Blocking DO Request Enable LTR Mechanism Enable End End TLP Prefix Blocking Target Link Speed Clock Power Management Compliance SOS Hardware Autonomous Width Hardware Autonomous Speed ...

Page 46: ... 6 USB Configuration Figure 3 16 USB Configuration Legacy USB Support XHCI Hand off USB Mass Storage Driver Support USB transfer time out Device reset time out Device power up delay AMI Virtual CDROMO 1 00 AMI Virtual HDISK0 1 00 ...

Page 47: ...37 SOM 5993 User Manual Chapter 3 AMI BIOS 3 4 7 Network Stack Configuration Figure 3 17 Network Stack Configurations Network Stack 3 4 8 NVMe Configuration Figure 3 18 NVMe Configuration ...

Page 48: ...creen You can select the items by highlighting it using by the Arrow keys All Plug and Play BIOS Setup options are described in this section The Plug and Play BIOS Setup screen is shown below Displays and provides option to change the Processor Settings Figure 3 19 Chipset Socket Configuration Platform Configuration ...

Page 49: ...39 SOM 5993 User Manual Chapter 3 AMI BIOS 3 5 1 Socket Configuration Figure 3 20 Socket Configuration Processor Configuration IIO Configuration Advanced Power Management Configuration Memory Topology ...

Page 50: ...SOM 5993 User Manual 40 3 5 1 1 Processor Configuration Figure 3 21 Processor Configuration Figure 3 22 Processor Configuration ...

Page 51: ...ory Skip Flex Ratio Override Check CPU BIST Result 3StrikerTimer Fast String Machine Check Max CPUID Value Limit Hardware Prefetcher Adjacent Cache Prefetch DCU Streamer Prefetcher DCU IP Prefetcher LLC Prefetcher DCU Mode Bsp Selection Extended APIC APIC Physical Mode PECI Legacy Agent SMBus Agent IS Agent Generic Agent eSPI Agent DBP F ...

Page 52: ...ery VMX Enable SMX Lock Chipset MSR Lock Control PKG CST CONFIG CONTOLR MSR Lock PPIN Control AES NI TSC Reset AC Exception On Split Lock Total Memory Encryption TME Limit CPU PA to 46 bits PSMI Configuration RDT CAT Opportunistic Tuning Per Socket Configuration Figure 3 24 Per Socket Configuration CPU Socket 0 Configuration ...

Page 53: ...43 SOM 5993 User Manual Chapter 3 AMI BIOS CPU Socket 0 Configuration Figure 3 25 CPU Socket 0 Configuration Core Disable Bitmap Hex ...

Page 54: ...SOM 5993 User Manual 44 PSMI Configuration Figure 3 26 PSMI Configuration Global PSMI Enable Socket 0 Configuration ...

Page 55: ...45 SOM 5993 User Manual Chapter 3 AMI BIOS Socket 0 Configuration Figure 3 27 Socket 0 Configuration PSMI Enabled ...

Page 56: ...t0 Configuration PCIe Train by BIOS NTB Link Train by BIOS Delay before link training PCIe Hot Plug Mask PCIe RP warm reset MCA PCIe Low Latency Retimers Skip PCIe retimers detection PCI E Completion Timerout PCI E Completion Timerout PCI E ASPM Support Global PCIe Max Read Request Size ...

Page 57: ...apter 3 AMI BIOS Socket0 Configuration Figure 3 29 Socket0 Configuration IOU0 IIO PCIe Port 1 Sck0 RP Correctable Err Sck0 RP NonFatal Uncorrectable Err Sck0 RP Fatal Uncorrectable Err TraceHub Configuration Menu R Link Port 1A ...

Page 58: ...SOM 5993 User Manual 48 TraceHub Configuration Menu Figure 3 30 TraceHub Configuration Menu North Trace Hub Enable Mode R Link Figure 3 31 R Link ...

Page 59: ...phasis PCI E Port Clocking PCI E Port Clock Gating Data Link Feature Exchange DMI Port MPSS PCI E Port D state PCI E Completion Timeout PCI E ASPM Support MSI PCI E Extend Sync Compliance Mode EOI Unsupported Request Alternate TxEq Alt ATTEN Table SRIS ECRC Generation ECRC Check SERRE MCTP ...

Page 60: ...SOM 5993 User Manual 50 Port 1A Figure 3 33 Port 1A ...

Page 61: ...s PCI E Port Clocking PCI E Port Clock Gating Data Link Feature Exchange DMI Port MPSS PCI E Port D state PCI E Completion Timeout PCI E ASPM Support MSI PCI E Extend Sync Compliance Mode EOI Unsupported Request Alternate TxEq Alt ATTEN Table SRIS ECRC Generation ECRC Check SERRE MCTP ...

Page 62: ...SOM 5993 User Manual 52 3 5 1 3 Advanced Power Management Configuration Figure 3 35 Advanced Power Management Configuration CPU P State Control CPU C State Control Package C State Control ...

Page 63: ...M 5993 User Manual Chapter 3 AMI BIOS CPU P State Control Figure 3 36 CPU P State Configuration SpeedStep Pstates Boot performance mode Energy Efficient Turbo Turbo Mode CPU Flex Ratio Override Perf P Limit ...

Page 64: ...SOM 5993 User Manual 54 Perf P Limit Figure 3 37 Perf P Limit Perf P Limit Differential Perf P Limit Clip Perf P Limit Threshold ...

Page 65: ... 5993 User Manual Chapter 3 AMI BIOS CPU C State Control Figure 3 38 CPU C State Configuration Enable Monitor MWAIT CPU C1 auto demotion CPU C1 auto undemotion CPU C6 report Enhanced Halt State C1E OS ACPI CX ...

Page 66: ...C State Control Package C State Register Access Low Latency Mode Disabled C2C3TT Dynamic L1 PKG C state Lat Neg LTR IIO Input Latency Tolerance Requirement LTR Enable PKGC_SA_PS_CRITERIA PKGC SA PS Criteria Power Management Control MDLL Off PKGc Interrupt Response Time ...

Page 67: ...57 SOM 5993 User Manual Chapter 3 AMI BIOS Latency Tolerance Requirement LTR Figure 3 40 Latency Tolerance Requirement LTR PCIe LTR Override Control ...

Page 68: ...SOM 5993 User Manual 58 PkgC SA PS Criteria Power Management Control Figure 3 41 PkgC SA PS Criteria Power Management Control CPU0 PKGC_SA_PS_CRITERIA ...

Page 69: ...59 SOM 5993 User Manual Chapter 3 AMI BIOS CPU0 PKGC_SA_PS_CRITERIA Figure 3 42 CPU0 PKGC_SA_PS_CRITERIA CPU0 Logical_ip_type PKGC_CRITERIA KTI ...

Page 70: ...SOM 5993 User Manual 60 PKGc Interrupt Response Time Figure 3 43 PKGc Interrupt Response Time VALID VALID VALID ...

Page 71: ...61 SOM 5993 User Manual Chapter 3 AMI BIOS 3 5 1 4 Memory Topology Figure 3 44 Memory Topology ...

Page 72: ...SOM 5993 User Manual 62 3 5 2 Platform Configuration Figure 3 45 Platform Configuration PCH IO Configuration System Event Log ...

Page 73: ...BIOS 3 5 2 1 PCH IO Configuration Figure 3 46 PCH IO Configuration PCI Express Configuration Fia Mux Configuration SATA Configuration USB Configuration Security Configuration State After G3 Pcie Pll SSC Flash Protection Range Registers FPRR ...

Page 74: ...Test Mode PCI Express Root Port 1 PCI Express Root Port 2 PCI Express Root Port 3 PCI Express Root Port 4 PCI Express Root Port 5 PCI Express Root Port 6 PCI Express Root Port 7 PCI Express Root Port 8 PCI Express Root Port 9 PCI Express Root Port 10 PCI Express Root Port 11 PCI Express Root Port 12 ...

Page 75: ...65 SOM 5993 User Manual Chapter 3 AMI BIOS PCI Express Root Port 1 Figure 3 48 PCI Express Root Port 1 PCI Express Root Port 1 ASPM L1 Substates Hot Plug PCIe Speed ...

Page 76: ...SOM 5993 User Manual 66 PCI Express Root Port 2 Figure 3 49 PCI Express Root Port 2 PCI Express Root Port 2 ASPM L1 Substates Hot Plug PCIe Speed ...

Page 77: ...67 SOM 5993 User Manual Chapter 3 AMI BIOS PCI Express Root Port 3 Figure 3 50 PCI Express Root Port 3 PCI Express Root Port 3 ASPM L1 Substates Hot Plug PCIe Speed ...

Page 78: ...SOM 5993 User Manual 68 PCI Express Root Port 4 Figure 3 51 PCI Express Root Port 4 PCI Express Root Port 4 ASPM L1 Substates Hot Plug PCIe Speed ...

Page 79: ...69 SOM 5993 User Manual Chapter 3 AMI BIOS PCI Express Root Port 5 Figure 3 52 PCI Express Root Port 5 PCI Express Root Port 5 ASPM L1 Substates Hot Plug PCIe Speed ...

Page 80: ...SOM 5993 User Manual 70 PCI Express Root Port 6 Figure 3 53 PCI Express Root Port 6 PCI Express Root Port 6 ASPM L1 Substates Hot Plug PCIe Speed ...

Page 81: ...71 SOM 5993 User Manual Chapter 3 AMI BIOS PCI Express Root Port 7 Figure 3 54 PCI Express Root Port 7 PCI Express Root Port 7 ASPM L1 Substates Hot Plug PCIe Speed ...

Page 82: ...SOM 5993 User Manual 72 PCI Express Root Port 8 Figure 3 55 PCI Express Root Port 8 PCI Express Root Port 8 ASPM L1 Substates Hot Plug PCIe Speed ...

Page 83: ...73 SOM 5993 User Manual Chapter 3 AMI BIOS PCI Express Root Port 9 Figure 3 56 PCI Express Root Port 9 PCI Express Root Port 9 ASPM L1 Substates Hot Plug PCIe Speed ...

Page 84: ...SOM 5993 User Manual 74 PCI Express Root Port 10 Figure 3 57 PCI Express Root Port 10 PCI Express Root Port 10 ASPM L1 Substates Hot Plug PCIe Speed ...

Page 85: ...75 SOM 5993 User Manual Chapter 3 AMI BIOS PCI Express Root Port 11 Figure 3 58 PCI Express Root Port 11 PCI Express Root Port 11 ASPM L1 Substates Hot Plug PCIe Speed ...

Page 86: ...SOM 5993 User Manual 76 PCI Express Root Port 12 Figure 3 59 PCI Express Root Port 12 PCI Express Root Port 12 ASPM L1 Substates Hot Plug PCIe Speed ...

Page 87: ...77 SOM 5993 User Manual Chapter 3 AMI BIOS Fia Mux Configuration Figure 3 60 Fia Mux Configuration Figure 3 61 Fia Mux Configuration ...

Page 88: ...SOM 5993 User Manual 78 Figure 3 62 Fia Mux Configuration Figure 3 63 Fia Mux Configuration ...

Page 89: ...Bifurcation FIA Mux Configuration Override FIA Mux Configuration Invalidate Lane 0 PCIe RP link width Lane 1 PCIe RP link width Lane 2 PCIe RP link width Lane 3 PCIe RP link width Lane 4 PCIe RP link width Lane 5 Lane 6 PCIe RP link width Lane 7 Lane 8 PCIe RP link width Lane 9 PCIe RP link width Lane 10 PCIe RP link width ...

Page 90: ...width Lane 13 PCIe RP link width Lane 14 PCIe RP link width Lane 15 PCIe RP link width Lane 16 PCIe RP link width Lane 17 Lane 18 Lane 19 Lane 20 Lane 21 Lane 22 Lane 23 SATA Configuration Figure 3 65 SATA Configuration SATA Controller Speed Controller 3 SATA Configuration ...

Page 91: ...81 SOM 5993 User Manual Chapter 3 AMI BIOS Controller 3 SATA Configuration Figure 3 66 Controller 3 SATA Configuration SATA Configuration Aggressive LPM Support Port 2 Port 3 ...

Page 92: ...SOM 5993 User Manual 82 USB Configuration Figure 3 67 USB Configuration USB Port Disable Override ...

Page 93: ...83 SOM 5993 User Manual Chapter 3 AMI BIOS Security Configuration Figure 3 68 Security Configuration BIOS Lock ...

Page 94: ...ar Viral Status Cloak Devhide registers from being accessible from OS System Cloaking FatalErrDebugHalt Mca Bank Warm Boot Clear Errors CrashLog Feature CrashLog On All Reset Shutdown Suppression eMCA Settings Whea Settings Error Injection Settings Memory Error Enabling IIO Error Enabling PCIe Error Enabling Error Control Setting ...

Page 95: ...ttings Figure 3 70 eMCA Settings EMCA Logging Support LMCE Support Ignore OS EMCA Opt in EMCA CMCI SMI Morphing EMCA CMCI SMI Threshold CSMI Dynamic Disable EMCA MCE SMI Enable Corrected Error elog Memory Error elog Processor Error elog Ubox Error Mask ...

Page 96: ...SOM 5993 User Manual 86 Whea Settings Figure 3 71 Whea Settings WHEA Support Whea Log Memory Error Whea Log Processor Error Whea Log PCI Error ...

Page 97: ...87 SOM 5993 User Manual Chapter 3 AMI BIOS Error Injection Settings Figure 3 72 Error Injection Settings WHEA Error Injection Support ...

Page 98: ...SOM 5993 User Manual 88 Memory Error Enabling Figure 3 73 Memory Error Enabling Memory Error Memory Corrected Error Spare Interrupt ...

Page 99: ...89 SOM 5993 User Manual Chapter 3 AMI BIOS IIO Error Enabling Figure 3 74 IIO Error Enabling Figure 3 75 IIO Error Enabling IIO PCH Global Error Support Os Native AER Support ...

Page 100: ...exprsp IIO IRPO csr acc 32b unaligned IIO IRPO wrcache uncecccso error IIO IRPO wrcache uncecccsi error IIO IRPO protocol rcvd poison error IIO IRPO wrcache correcccso error IIO IRPO wrcache correcccsi error IIO Misc Error IIO Vtd Error IIO Dma Error IIO Dmi Error PCIE Error IIO PCIE Additional Corrected Error IIO PCIE Additional Uncorrected Error IIO PCIE Additional Received Completion With UR II...

Page 101: ...91 SOM 5993 User Manual Chapter 3 AMI BIOS PCIe Error Enabling Figure 3 76 PCIe Error Enabling Figure 3 77 PCIe Error Enabling Corrected Error Uncorrected Error ...

Page 102: ...l Error PCIE Unsupported Request Error PCIE Surprise Link Down Error Assert NMI On SERR Assert NMI ON PERR Expected BER Time Window Gen1 2 Time Window Gen3 4 Error Threshold Gen1 2 Error Threshold Gen3 4 Gen3 4 Re Equalization Gen2 Link Degradation Gen3 Link Degradation Gen4 Link Degradation Error Control Setting Figure 3 78 Error Control Setting Latch First Corrected Error in KTI Partrol Scrub Er...

Page 103: ...93 SOM 5993 User Manual Chapter 3 AMI BIOS 3 6 Server Mgmt Figure 3 79 Server Mgmt BMC Support ...

Page 104: ...SOM 5993 User Manual 94 3 7 Security Figure 3 80 Security Administration Password User Password Secure Boot ...

Page 105: ...95 SOM 5993 User Manual Chapter 3 AMI BIOS 3 7 1 Secure Boot Figure 3 81 Secure Boot Secure Boot Secure Boot Mode ...

Page 106: ...SOM 5993 User Manual 96 3 8 Boot Figure 3 82 Boot Setup Prompt Timeout Bootup Numlock State Quiet Boot Boot Option 1 ...

Page 107: ...MI BIOS 3 9 Save and Exit Figure 3 83 Save and Exit Save Changes and Exit Discard Changes and Exit Save Changes and Reset Discard Changes and Reset Save Changes Discard Changes Restore Defaults Save as User Defaults Restore User Defaults ...

Page 108: ...SOM 5993 User Manual 98 ...

Page 109: ...Chapter 4 4 S W Introduction Installation S W Introduction Driver Installation Advantech iManager ...

Page 110: ...are solu tions easily and widely available to the embedded computing community 4 2 Driver Installation The Intel Chipset Software Installation CSI utility installs the Windows INF files that outline to the operating system how the chipset components will be configured 4 3 Windows Driver Setup To install the drivers on a windows based operation system please connect to the Internet and browse the w...

Page 111: ...th and provide an advanced watchdog to handle errors as they happen iManager also comes with a secure encrypted EEPROM for storing important security keys or other customer defined information All the embedded functions are configured through API and pro vide corresponding utilities These APIs comply with PICMG EAPI Embedded Appli cation Programmable Interface specifications and unify in the same ...

Page 112: ...SOM 5993 User Manual 102 ...

Page 113: ...Appendix A A Pin Assignment This appendix details information on the hardware pin assignment of the SOM 5993 CPU System on Module Sections include SOM 5993 Type 7 Pin Assign ment ...

Page 114: ...LPC_DRQ0 A9 GBE0_MDI1 B9 LPC_DRQ1 A10 GBE0_MDI1 B10 LPC_CLK A11 GND FIXED B11 GND FIXED A12 GBE0_MDI0 B12 PWRBTN A13 GBE0_MDI0 B13 SMB_CK A14 GBE0_CTREF B14 SMB_DAT A15 SUS_S3 B15 SMB_ALERT A16 SATA0_TX B16 SATA1_TX A17 SATA0_TX B17 SATA1_TX A18 SUS_S4 B18 SUS_STAT A19 SATA0_RX B19 SATA1_RX A20 SATA0_RX B20 SATA1_RX A21 GND FIXED B21 GND FIXED A22 PCIE_TX15 B22 PCIE_RX15 A23 PCIE_TX15 B23 PCIE_RX1...

Page 115: ...D FIXED B60 GND FIXED A61 PCIE_TX2 B61 PCIE_RX2 A62 PCIE_TX2 B62 PCIE_RX2 A63 GPI1 B63 GPO3 A64 PCIE_TX1 B64 PCIE_RX1 A65 PCIE_TX1 B65 PCIE_RX1 A66 GND B66 WAKE0 A67 GPI2 B67 WAKE1 A68 PCIE_TX0 B68 PCIE_RX0 A69 PCIE_TX0 B69 PCIE_RX0 A70 GND FIXED B70 GND FIXED A71 PCIE_TX8 B71 PCIE_RX8 A72 PCIE_TX8 B72 PCIE_RX8 A73 GND B73 GND A74 PCIE_TX9 B74 PCIE_RX9 A75 PCIE_TX9 B75 PCIE_RX9 A76 GND B76 GND A77...

Page 116: ...6 VCC_12V A107 VCC_12V B107 VCC_12V A108 VCC_12V B108 VCC_12V A109 VCC_12V B109 VCC_12V A110 GND FIXED B110 GND FIXED SOM 5993 ROW C D C1 GND FIXED D1 GND FIXED C2 GND D2 GND C3 USB_SSRX0 D3 USB_SSTX0 C4 USB_SSRX0 D4 USB_SSTX0 C5 GND D5 GND C6 USB_SSRX1 D6 USB_SSTX1 C7 USB_SSRX1 D7 USB_SSTX1 C8 GND D8 GND C9 USB_SSRX2 D9 USB_SSTX2 C10 USB_SSRX2 D10 USB_SSTX2 C11 GND FIXED D11 GND FIXED C12 USB_SSR...

Page 117: ... C42 10G_KR_RX1 D42 10G_KR_TX1 C43 10G_KR_RX1 D43 10G_KR_TX1 C44 GND D44 GND C45 D45 C46 CEI_MDC D46 CEI_MDIO C47 10G_INT0 D47 C48 GND D48 GND C49 10G_KR_RX0 D49 10G_KR_TX0 C50 10G_KR_RX0 D50 10G_KR_TX0 C51 GND FIXED D51 GND FIXED C52 PEG_RX0 D52 PEG_TX0 C53 PEG_RX0 D53 PEG_TX0 C54 GND D54 C55 PEG_RX1 D55 PEG_TX1 C56 PEG_RX1 D56 PEG_TX1 C57 NC D57 GND C58 PEG_RX2 D58 PEG_TX2 C59 PEG_RX2 D59 PEG_TX...

Page 118: ... D88 PEG_TX11 C89 PEG_RX11 D89 PEG_TX11 C90 GND FIXED D90 GND FIXED C91 PEG_RX12 D91 PEG_TX12 C92 PEG_RX12 D92 PEG_TX12 C93 GND D93 GND C94 PEG_RX13 D94 PEG_TX13 C95 PEG_RX13 D95 PEG_TX13 C96 GND D96 GND C97 RSVD D97 RSVD C98 PEG_RX14 D98 PEG_TX14 C99 PEG_RX14 D99 PEG_TX14 C100 GND FIXED D100 GND FIXED C101 PEG_RX15 D101 PEG_TX15 C102 PEG_RX15 D102 PEG_TX15 C103 GND D103 GND C104 VCC_12V D104 VCC_...

Page 119: ...Appendix B B Watchdog Timer This appendix details information regarding the watchdog timer programming for the SOM 5993 CPU System on Module Sections include Watchdog Timer Programming ...

Page 120: ...and then set to EC Only Win8 1 and Win10 support it In other OS it will still use IRQ number from BIOS setting as usual For details please refer to iManager Software API User Manual Trigger Event Note IRQ IRQ5 7 14 BIOS setting default disable NMI N A SCI Power button event Power Off Support H W Restart Support WDT Pin Activate Support ...

Page 121: ...Appendix C C Programming GPIO This appendix provides a General Purpose Input and Output pin set ting diagram Sections include System I O ports ...

Page 122: ...3 User Manual 112 C 1 GPIO Register For details please refer to iManager Software API User Manual GPIO Byte Mapping H W Pin Name BIT0 GPO0 BIT1 GPO1 BIT2 GPO2 BIT3 GPO3 BIT4 GPI0 BIT5 GPI1 BIT6 GPI2 BIT7 GPI3 ...

Page 123: ...em Assignments This appendix details information on the system resource alloca tion of the SOM 5993 CPU System on Module Sections include System I O Ports DMA Channel Assignments Interrupt Assignments 1st MB Memory Map ...

Page 124: ...resources 0x00000089 0x0000008B Direct memory access controller 0x0000008C 0x0000008E Motherboard resources 0x0000008F 0x0000008F Direct memory access controller 0x00000090 0x0000009F Motherboard resources 0x000000A0 0x000000BD Programmable interrupt controller 0x000000C0 0x000000DF Direct memory access controller 0x000000F0 0x000000F0 Numeric data processor 0x00000200 0x0000027F Motherboard resou...

Page 125: ...00 0x00004FFF PCI Express to PCI PCI X Bridge 0x00004000 0x00004FFF ASPEED Graphics Family WDDM 0x00005000 0x0000501F CDF LegacySMBus 18DF 0x00005020 0x0000503F Standard SATA AHCI Controller 0x00005040 0x00005047 CDF HSUART 18D8 0x00005050 0x00005057 CDF HSUART 18D8 0x00005060 0x00005067 CDF HSUART 18D8 0x00005070 0x00005073 Standard SATA AHCI Controller 0x00005080 0x00005087 Standard SATA AHCI Co...

Page 126: ...A7 IRQ 4294967294 CDF PCIeRP 2 18A6 Table D 4 1st MB Memory Map Addr Range Hex Device 0x90000000 0xB3FFFFFF PCI Express Root Complex 0xA0000 0xBFFFF CDF PCIeRP 2 18A6 0xA0000 0xBFFFF PCI Express Root Complex 0xA0000 0xBFFFF PCI Express to PCI PCI X Bridge 0xAC000000 0xB00FFFFF CDF PCIeRP 2 18A6 0xAC000000 0xB00FFFFF PCI Express to PCI PCI X Bridge 0xAC000000 0xB00FFFFF ASPEED Graphics Family WDDM ...

Page 127: ...urces 0xFE010000 0xFE010FFF CDF SPI 18E0 0xFE010000 0xFE010FFF PCI Express Root Complex 0xFE200000 0xFE7FFFFF Motherboard resources 0xFEC00000 0xFECFFFFF Advanced programmable interrupt controller 0xFED00000 0xFED003FF High precision event timer 0xFED40000 0xFED44FFF Trusted Platform Module 2 0 0xFF000000 0xFFFFFFFF Motherboard resources 0xFF000000 0xFFFFFFFF Motherboard resources 0xFFA00000 0xFFA...

Page 128: ...re subject to change without notice No part of this publication may be reproduced in any form or by any means such as electronically by photocopying recording or otherwise without prior written permission from the publisher All brand and product names are trademarks or registered trademarks of their respective companies Advantech Co Ltd 2022 ...

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