１１５
Signal
Pin#
Description
I/O
Note
PWR_OK
B24
Power OK from main power supply. A high value indicates
that the power is good. This signal can be used to hold off
Module startup to allow Carrier based FPGAs or other
configurable devices time to be programmed.
Carrier Board:
Connect to power good pin of main power supply ATX -
PW-OK pin 8 of ATX power connector connects 3.3V level
shifter to COME PWR_OK.
AT - PG pin P8.1 of AT power connector connects 3.3V
level shifter to COME PWR_OK.
Other - PWROK of 12V power generator circuit connects
3.3V level shifter to COME PWR_OK.
N/C is not allowed, if the system is ATX mode.
N/C if not used.
I 3.3V
CMOS
SUS_STAT#
/ESPI_RESET#
B18
Indicates imminent suspend operation; used to notify
LPC devices. Not used in eSPI implementations.
Carrier Board:
Connect to LPCPD# of LPC device.
N/C if not used.
O 3.3V
Suspend
CMOS
SUS_S3#
A15
Indicates system is in Suspend to RAM state. Active low
output. An inverted copy of SUS_S3# on the Carrier
Board
may
be used to enable the non-standby power
on a typical ATX supply.
Carrier Board:
Connect to SLP_S3# (Suspend To RAM) of LPC device or
SIO.
N/C if not used.
O 3.3V
Suspend
CMOS
SUS_S4#
A18
S4 Sleep control signal indicating that the system resides
in S4 state (Suspend to Disk).
Carrier Board:
Connect to SLP_S4# (Suspend To Disk) of LPC device or
SIO.
N/C if not used.
O 3.3V
Suspend
CMOS
SUS_S5#
A24
S5 Sleep Control signal indicating that the system resides
in S5 State (Soft Off).
Carrier Board:
Connect to SLP_S5# (Soft Off) of LPC device or SIO.
N/C if not used.
O 3.3V
Suspend
CMOS
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