71
2.7.2.1 USB 2.0 General Design Considerations and Optimization
Use the following general routing and placement guidelines when laying out a new design. These
guidelines help minimize signal quality and EMI problems.
• Do not route USB 2.0 traces under crystals, oscillators, clock synthesizers, magnetic devices or ICs
that use and/or duplicate clocks.
• Separate signal traces into similar categories, and route similar signal traces together (such as routing
differential-pairs together).
• Keep USB 2.0 signals clear of the core logic set. High current transients are produced during internal
state transitions and can be very difficult to filter out.
• Follow the 20 x h rule by keeping traces at least [20 x (height above the plane)] mils away from the
edge of the plane (VCC or GND). For an example stackup, the height above the plane is 4.5 mils (0.114
mm). This calculates to a 90-mil (2.286-mm) spacing requirement from the edge of the plane. This
helps prevent the coupling of the signal onto adjacent wires and also helps prevent free radiation of the
signal from the edge of the PCB.
• Avoid stubs on high-speed USB signals because stubs cause signal reflections and affect signal quality.
If a stub is unavoidable in the design, the total of all the stubs on a particular line should not be greater
than 200 mils (5.08 mm).
2.7.2.2 USB 2.0 Port Power Delivery
The following is a suggested topology for power distribution of VBUS to USB ports.
These circuits provide two types of protection during dynamic attach and detach situations on the bus:
inrush current limiting (droop) and dynamic detach flyback protection. These two types require both bulk
capacitance (droop) and filtering capacitance (for dynamic detach flyback voltage filtering).
Intel
recommends the following:
• Minimize the inductance and resistance between the coupling capacitors and the USB ports.
• Place capacitors as close as possible to the port and the power-carrying traces should be as wide as
possible, preferably, a plane.
• Make the power-carrying traces wide enough that the system fuse blows on an over current event. If
the system fuse is rated at 1 A, then the power-carrying traces should be wide enough to carry at least
1.5 A.