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PCIE-1816_1816H User Manual

42

Single Clock Source Driving 

Single  clock  source  driving  is  a  specific  function  well-suited  for  consecutive  data
acquisition while there is only one clock signal available. CONV CLKs will be inter-
nally routed as SCAN CLKs. And the external SCAN CLKs input will not be accepted.
Figure describes how it works. 

Summary of Contents for PCIE-1816

Page 1: ...User Manual PCIE 1816 1816H 16 bit Multi function Card with PCI Express Bus ...

Page 2: ...r installation Advantech assumes no liability under the terms of this warranty as a consequence of such events Because of Advantech s high quality control standards and rigorous testing most of our customers never need to use our repair service If an Advantech product is defec tive it will be repaired or replaced at no charge during the warranty period For out of warranty repairs you will be bille...

Page 3: ...chments Description of your software operating system version application software etc A complete description of the problem The exact wording of any error messages Packing List Before setting up the system check that the items listed below are included and in good condition If any item does not accord with the table Contact your dealer imme diately PCIE 1816 1816H DA C card Startup or User Manual...

Page 4: ...PCIE 1816_1816H User Manual iv ...

Page 5: ... Configuration after Hot Reset JP1 15 3 2 3 Jumper Settings to Set Ports as Software configurable or Output ports 16 Table 3 3 Function Description 16 3 3 Signal Connections 17 Figure 3 2 68 pin I O Connector Pin Assignments 17 3 3 1 I O Connector Signal Description 18 Table 3 4 I O Connector Signal Descriptions 18 3 3 2 Analog Input Connections 19 Figure 3 3 Single ended input channel connections...

Page 6: ...le B 1 Gains and Analog Input Range 39 B 1 3 Analog Input Acquisition Mode 39 B 1 4 AI Trigger Modes 43 B 1 5 AI SCAN CONV Clock Source 46 B 1 6 AI Trigger Source 47 Table B 2 Analog Input Data Format 47 Table B 3 Full Scale Values for Input Voltage Ranges 48 B 2 PCIE 1816 1816H Analog Output Operation 48 B 2 1 Analog Output Ranges 48 B 2 2 Analog Output Operation Modes 49 B 2 3 AO Clock Sources 5...

Page 7: ...Chapter 1 1 Introduction This chapter introduces PCIE 1816 1816H and and its typical applications Sections include Features Applications Installation Guide Software Overview Roadmap Accessories ...

Page 8: ...le Programmable gain for each input channel automatic channel gain scanning 4K onboard ring buffer for analog input and output Two independent 16 bit analog output channels with continuous waveform out put function of maximum 3 MHz throughput rate Auto Calibration for analog input and output channels 24 digital Input or output channels TTL compatible Two 32 bit independent full function counters B...

Page 9: ...sient analysis 1 3 Installation Guide Before you install your PCIE 1816 1816H card please make sure you have the fol lowing necessary components PCIE 1816 1816H DA C card PCIE 1816 1816H User Manual Driver software Advantech DAQNavi software included in the companion DVD ROM Personal computer or workstation with a PCI Express interface running Win dows 8 desktop mode 7 and XP Shielded Cable PCL 10...

Page 10: ...PCIE 1816_1816H User Manual 4 Figure 1 1 Installation Flow Chart ...

Page 11: ...on from scratch using Advantech DAQNavi Device Driver with your favorite develop ment tools such as Visual Studio Net Visual C Visual Basic Delphi and C Builder The step by step instructions on how to build your own applications using each development tool will be given in the Device Drivers Manual Moreover a set of example source code is also given for your reference Programming Tools Programmers...

Page 12: ... Function Group For the usage and parameters of each function please refer to the Using DAQNavi SDK chapter in the DAQNavi SDK Manual Troubleshooting DAQNavi Device Drivers Error Driver functions will return a status code when they are called to perform a certain task for the application When a function returns a code that is not zero it means the function has failed to perform its designated func...

Page 13: ...pter provides a packaged item checklist proper instructions for unpacking and step by step procedures for both driver and card installation Sections include Unpacking Driver Installation Hardware Installation Device Setup Configuration ...

Page 14: ...Touch the anti static bag to a metal part of your computer chassis before open ing the bag Take hold of the card only by the metal bracket when removing it out of the bag After taking out the card you should first Inspect the card for any possible signs of external damage loose or damaged components etc If the card is visibly damaged please notify our service department or our local sales represen...

Page 15: ...ll be launched automatically if you have the autoplay func tion enabled on your system When the Setup Program is launched you will see the following Setup Screen Figure 2 1 Setup Screen of Advantech Automation Software 3 Select the Installation option 4 Select the Legacy SDK and Drivers option to install 5 Select the Individual Drivers option 6 Select the PCIE series and the specific device then f...

Page 16: ...ur computer before installing or removing any components on the computer 2 Remove the cover of your computer 3 Remove the slot cover on the back panel of your computer 4 Touch the metal part on the surface of your computer to neutralize the static electricity that might be on your body 5 Insert the PCIE 1816 1816H card into the PCI Express interface Hold the card only by its edges and carefully al...

Page 17: ... Navigator program is a utility that allows you to set up configure and test your device and later stores your settings on the system registry These settings will be used when you call the APIs of Advantech Device Drivers Setting Up the Device 1 To install the I O device for your card you must first run the Advantech Naviga tor program by accessing Start Programs Advantech Automation DAQNavi Advan...

Page 18: ... but also Digital Input Output Figure 2 4 The Device Setting page 4 After your card is properly installed and configured you can go to the Device Test page to test your hardware by using the testing utility supplied Figure 2 5 The Device Testing of PCIE 1816 1816H For more detailed information please refer to the DAQNavi SDK Manual or the User Interface Manual in the Advantech Navigator ...

Page 19: ...ns This chapter provides useful information about how to connect input and output signals to the PCIE 1816 1816H card via the I O connector Sections include Overview BoardID Settings Signal Connections Field Wiring Considerations ...

Page 20: ...y A good signal con nection can avoid unnecessary and costly damage to your PC and other hardware devices This chapter provides useful information about how to connect input and output signals to the PCIE 1816 1816H card via the I O connector 3 2 Switch and Jumper Settings Please refer to Figure 3 1 for jumper and switch locations on PCIE 1816 1816H Figure 3 1 Connector and Switch Locations ...

Page 21: ... input and analog output channels to open status the current of the load can t be sink so that the external devices will not be damaged when the system starts or resets When the system is hot reset then the status of isolated digital output channels are selected by jumper JP1 Table 3 2 shows the configuration of jumper JP1 Table 3 1 Board ID Setting SW1 SW1 Position 1 Position 2 Position 3 Positio...

Page 22: ...configurable or Output ports Table 3 3 Function Description Set DIO channel as software configurable input or output default Set DIO channel as output Jumper number Relative channels JP1600 DIO 0 3 JP1601 DIO 4 7 JP1700 DIO 8 11 JP1701 DIO 12 15 JP1800 DIO 16 19 JP1801 DIO 20 23 ...

Page 23: ... PCIE 1816 1816H is a 68 pin connector that enable you to connect to accessories with the PCL 10168 1 or PCL 10168H shielded cable Figure 3 2 shows the pin assignments for the 68 pin I O connector on the PCIE 1816 1816H and Table 3 3 shows its I O connector signal description Figure 3 2 68 pin I O Connector Pin Assignments ...

Page 24: ...ND Input AI Scan Clock This pin is used to initiate a set of data acquisition The card samples the AI signals of every channel in the scan list once for every AI Scan Clock AI_CONV DGND Input AI Conversion Clock This pin is to initiate a sin gle AI conversion on a single channel A Scan controlled by the AI Scan Clock consists of one or more conversions AO0_REF AO1_REF AGND Input AO Channel 0 1 Ext...

Page 25: ... reference ground for external floating signal sources Figure 3 3 shows a single ended channel connection between a floating signal source and an input channel Figure 3 3 Single ended input channel connections When to Use Single ended Channel Connections Single ended connections are only used for the following conditions All input signals that can share a common reference point AGND The wire conne...

Page 26: ...re the ground of the signal source and the ground of the card will not be exactly of the same voltage The difference between the ground volt ages forms a common mode voltage Vcm To avoid the ground loop noise effect caused by common mode voltages you can connect the signal ground to the Low input Figure 3 4 shows a differential channel connection between a ground reference signal source and an inp...

Page 27: ... You must therefore reference the sig nal source against the AGND Figure 3 5 shows a differential channel connection between a floating signal source and an input channel on the PCI 1816 1816H In this figure each side of the floating signal source is connected through a resistor to the AGND This connection can reject the common mode voltage between the signal source and the PCI 1816 1816H ground F...

Page 28: ... sample clock uses a 100 MHz time base Conversions start on the ris ing edge of the counter output You can use software to specify the clock source as internal and the sampling frequency to pace the operation The minimum frequency is 0 024 S s the maximum frequency is 500 KS s According to the sampling theory Nyquist Theorem you must specify a frequency that is at least twice as fast as the input ...

Page 29: ...ck input signal You can use software to specify the clock source as exter nal The sampling frequency is always limited to a maximum of 10 MHz for the exter nal AI sample clock input signal Figure 3 6 External Clock Source Connection Trigger Sources Connections External Digital TTL Trigger For analog input operations an external digital trigger event occurs when the PCIE 1816 1816H detects either a...

Page 30: ...RG0 and ATRG1 On the PCIE 1816 1816H the threshold level is set using a dedicated 16 bit DAC By software you can program the threshold level by writing a voltage value to this DAC this value can range from 10V to 10V Figure 3 8 External Analog Trigger Source Connection Analog Output Connection The PCIE 1816 1816H provides two AO output channels You can use the internal precision 5 V or 10 V refere...

Page 31: ...25 PCIE 1816_1816H User Manual Chapter 3 Signal Connections Fig 3 9 shows how to make analog output and external reference input connections on the PCIE 1816 1816H Figure 3 9 Analog Output Connections ...

Page 32: ...ls Connect an external AO output clock to the pin and then the conversions will start on input signal s rising edge You can use software to spec ify the clock source as external The maximum input clock frequency is 3MS s Figure 3 10 External Clock Source Connection Trigger Sources Connections External Digital TTL Trigger The PCIE 1816 1816H supports External digital TTL trigger to activate AO conv...

Page 33: ...CIE 1816H the threshold level is set using a dedicated 16 bit DAC By software you can program the threshold level by writing a voltage value to this DAC this value can range from 10V to 10V Figure 3 12 External Analog Trigger Source Connection 3 3 3 Digital Signal Connections The PCIE 1816 1816H has 24 digital input output channels and they can be config ured as input or output channels The digita...

Page 34: ...ual 28 Figure 3 14 Wet signal connection of digital input Figure 3 15 Dry signal connection of digital input Digital Output Connections PCIE 1816 1816H also has TTL digital output Figure 3 16 Digital Output Channel Connections ...

Page 35: ...ct a data acquisition system If the cable travels through an area with significant electromagnetic interference you should adopt individually shielded twisted pair wires as the analog input cable This type of cable has its signal wires twisted together and shielded with a metal mesh The metal mesh should only be connected to one point at the sig nal source ground Avoid running the signal cables th...

Page 36: ...PCIE 1816_1816H User Manual 30 ...

Page 37: ...Appendix A A Specifications ...

Page 38: ...PCIE 1816_1816H User Manual 32 A 1 Function Block ...

Page 39: ...4 4 4 4 3 3 1 7 Max Input Voltage 15 V Input Impedance 1G Ω 2pF Clock Source Software or external Trigger Mode Start trigger Delay to Start trigger Stop trigger Delay to Stop trigger Accuracy DC INLE 2 LSB Under manual adjustment DNLE 1 LSB Under manual adjustment Offset error Adjustable to zero Gain 0 5 1 2 4 8 Gain Error FSR 0 007 5 0 007 5 0 007 5 0 008 0 008 Channel Type Single Ended Different...

Page 40: ...put 10V x 10V Maximum Range 0 x V x V x V Accuracy Relative 1 LSB Differential Non Linearity 1 LSB monotonic Slew Rate 20 V μs Gain Error Adjustable to zero manual calibration Drift 30 ppm C Driving Capability 5 mA Update Mode Static update waveform Output Impedance max 0 1 Ω Capacitive max 500 pF Channels 24 shared TTL compatible Input Voltage Low 0 8V max High 2 0 V min Output Voltage Low 0 8 V ...

Page 41: ...uency 40KHz Pulse Width Measurement 0 1 when input signal frequency 40KHz Pulse Output within 2 when output frequency 1MHz PWM Output within 2 when output frequency 1MHz Note When performing advanced functions like frequency measurement and pulse output there will be errors And the error will vary depending on the parameter selections and the OS performance I O Connector Type 68 pin SCSI female Di...

Page 42: ...PCIE 1816_1816H User Manual 36 ...

Page 43: ...Appendix B B Operation Theory ...

Page 44: ...t data format B 1 1 AI Hardware Structure The AI conversion hardware structure includes four major parts Auto scan multiplexer routes the analog input signals into AI converter chan nel by channel in a software defined sequence PGIA Programmable Gain Instrument Amplifier rectifies the input range and amplify alleviate input signal to match the input range of A D converter AI converter conceives th...

Page 45: ...h channel cyclically The update rate is sampling rate num of active channels Buffer Mode Adopt buffer mode to acquire data if you wanna accurately control the time interval between conversions AI conversion clocks come from internal clock sources or external signals on connector AI conversion starts when the clocks signal come in and will not stop if the clocks are continuously sent Conversion dat...

Page 46: ...fined as the time auto scan multiplexer routes input channels from Start channel to Stop channel once On the other words all the active channels are sam pled once in a single iteration After the iteration counter counts down to zero the Acquisition Window will be disable automatically and wait for the next incoming SCAN CLK The end of Acquisition Window resets the iteration counter to its user spe...

Page 47: ...41 PCIE 1816_1816H User Manual Appendix B Operation Theory Other scanning procedure applications timing diagram ...

Page 48: ...lock source driving is a specific function well suited for consecutive data acquisition while there is only one clock signal available CONV CLKs will be inter nally routed as SCAN CLKs And the external SCAN CLKs input will not be accepted Figure describes how it works ...

Page 49: ...ay trigger mode and about trigger mode and user can set it as the num ber of delay SCAN CLKs before trigger or the number of holding SCAN CLKs after trigger Figure shows the four different trigger modes Start Trigger Acquisition Mode Start trigger acquisition starts when the PCIE 1816 1816H detects the trigger event and stops when you stop the operation The SCAN CLKs before Trigger will be blocked...

Page 50: ...Acquisition Mode When you want to acquire data both before and after a specific trigger event occurs users should take advantage of the delay to stop trigger mode First designate the size of the allocated memory and the amount of samples to be snatched after the trigger event happens The trigger acquisition starts when the first SCAN CLK signal comes in Once a trigger event happens the on going da...

Page 51: ...tion Mode Stop trigger mode is a particular application of about trigger mode Use pre trigger acquisition mode when you want to acquire data before a specific trigger event occurs Stop trigger acquisition starts when you start the operation and stops when the trigger event happens ...

Page 52: ... internal AI SCAN clock or when you want to pace at uneven intervals Acquisitions will start the rising edge of the external AI SCAN clock input And the frequency for PCIE 1816 and PCIE 1816H should be always limited under 500 KHz and 1 MHz The exceeding frequency may result in data loss or unexpected data acquisition External AI CONV clock This setting is useful when single external clock source ...

Page 53: ... PCIE 1816 1816H detects either a rising or falling edge on the External AI TTL trigger input The trigger signal is TTL compatible Analog Threshold Trigger For analog input operations an analog trigger event occurs when the PCIE 1816 1816H detects a transition from above a threshold level to below a threshold level falling edge or a transition from below a threshold level to above a threshold leve...

Page 54: ... PCIE 1816 1816H provides two 16 bit analog output channels both of which can be configured internally to be applicable within 0 5 V 0 10 V 5 V 10 V output voltage range Otherwise users can use external reference voltage to apply 0 x V or x V output range where the value x is from 10 to 10 Users can configure the output range during driver installation or in software programming Table B 3 Full Sca...

Page 55: ...antage of the PCIE 1816 1816H In this mode you can specify a clock and trigger source and either of the two analog output channels to work in this mode Before operating in this mode users need to set the clock and trigger source first and then generate the output data stored in the memory buffers of host PC The host computer then transfers that data to the DACs buffers on PCIE 1816 1816H When PCIE...

Page 56: ...ven intervals Connect an external AO output clock to the pin and then the conversions will start on input signal s rising edge You can use software to spec ify the clock source as external The maximum input clock frequency is 3 MS s B 2 4 AO Trigger Sources The PCIE 1816 1816H supports External digital TTL trigger to activate AO conver sions for waveform mode An external digital trigger event occu...

Page 57: ...d pulse width measurement Counters on PCIE 1816 1816H have a counter value match interrupt function When this interrupt function is enabled an interrupt signal will be generated if the counter value reaches a pre set counter match value The counter will continue to count until an overflow occurs then it will go back to its reset value zero and continue the count ing process A user can set each ind...

Page 58: ...value of the sig nal connected to counter input 3 Pulse Width measurement Connection PCIE 1816 1816H built in counter can measure the pulse width value of the sig nal connected to counter input The measurable range is 50 ns to 107 seconds You can measure both the logic high time and logic low time within the measur able range ...

Page 59: ...he internal clock is 20 MHz so PCIE 1816 1816H will periodically generate output signal and interrupt every 4 pulses of the internal clock 20 MHz 5 MHz 4 Available output frequency range is 0 005 Hz 5 MHz 5 Delay Pulse Generation Using PCIE 1816 1816H internal clock you can change the logic level within a specific period starting from a trigger signal connecting to counter gate input For example i...

Page 60: ...M Output PCIE 1816 1816H can generate PWM pulse width modulation signal which you can configure its logic high time and logic low time as figure below The available period range for logic high time and logic low time is 100 ns 214 second ...

Page 61: ...55 PCIE 1816_1816H User Manual Appendix B Operation Theory ...

Page 62: ...ations are subject to change without notice No part of this publication may be reproduced in any form or by any means electronic photocopying recording or otherwise without prior written permis sion of the publisher All brand and product names are trademarks or registered trademarks of their respective companies Advantech Co Ltd 2019 ...

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