Advantech PCIE-1805, User Manual

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33 PCIE-1805 User Manual
Appendix B
O
peration
Theory
B.1.4 AI CONV Clock Source
The PCIE-1805 can adopt both internal and external clock sources to accomplish
pacer acquisition. You can set the clock and trigger sources conveniently by soft-
ware. The figure can help you understand the routing route of clock and trigger gen-
eration.
CONV Clock
– Internal AI CONV clock derived from 32-bit divider
– External AI CONV clock from terminal board
 Internal AI CONV Clock
The internal AI CONV clock applies 100 MHz time base accompanied with 32-
bit divider. The maximum frequency is 250 KS/s. According to the sampling the-
ory (Nyquist Theorem), you must specify a frequency that is at least twice as
fast as the input’s highest frequency component to achieve a valid sampling. For
example, to accurately sample a 20 kHz signal, you have to specify a sampling
frequency of at least 40 kHz. This consideration can avoid an error condition
often know as aliasing, in which high frequency input components appear erro-
neously as lower frequencies when sampling.
 External AI CONV Clock
The external AI CONV Clock is convenient in uneven sampling internal. AI con-
version will start by each arriving rising edge. The sampling frequency is always
limited to a maximum of 250 KHz.