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43

Chapter 5  

Step 9a:

Once the 

Status

 indicates 

Failed

, please check if both the wiring 

and the input voltage are correct. When finished checking, click the 

Start

 

button again to restart the procedure, or click the 

Cancel

 button to stop 

the calibration.

Figure 5.10: Gain Calibration Failed

Step 10:

When the current channel is calibrated, click the 

Finish

 button to 

end the procedure. You can proceed to 

Step 3

 to select another channel 

for calibration, and repeat from 

Step 4

 to 

Step 9

, until the rest of the chan-

nels are all calibrated one after one. 

Figure 5.11: Calibration Procedure Completed

Summary of Contents for PCIE-1744

Page 1: ...PCIE 1744 30 MS s Simultaneous 4 ch Analog Input PCI Express Card User Manual...

Page 2: ...any means without the prior written permission of Advantech Co Ltd Information provided in this manual is intended to be accurate and reli able However Advantech Co Ltd assumes no responsibility for i...

Page 3: ...lacement materials service time and freight Please consult your dealer for more details If you think you have a defective product follow these steps 1 Collect all the information about the problem enc...

Page 4: ...peripheral attachments Description of your software operating system version appli cation software etc A complete description of the problem The exact wording of any error messages Packing List Befor...

Page 5: ...ction Library 8 1 5 3 Troubleshooting Device Drivers Error 8 1 6 Accessories 9 1 6 1 Wiring Cables 9 1 6 2 Wiring Boards 9 Chapter 2 Installation 12 2 1 Unpacking 12 2 2 Driver Installation 13 Figure...

Page 6: ...t Trigger Acquisition Mode 31 4 2 6 Pre Trigger Acquisition Mode 32 Figure 4 4 Pre Trigger Acquisition Mode 32 4 3 A D Sample Clock Sources 32 4 3 1 Internal A D Sample Clock 33 4 3 2 External A D Sam...

Page 7: ...ge Control 59 C 5 A D Converter Enable Write Read BASE A 59 Table C 7 Register for A D Converter Enable 59 C 6 Clock Source and Divider Write Read BASE C 60 Table C 8 Register for Clock Source and Div...

Page 8: ...ASE 2C 70 Table C 18 Register for BoardID Switch 70 C 17 Reset DMA Start Channel to CH0 Write BASE 30 70 Table C 19 Register for Reset DMA Start Channel to CH0 70 C 18 AD Channel n DATA Read BASE 30 3...

Page 9: ...de information on the features of the PCIE 1744 card a quick installation guide and informa tion on software and accessories Sections include Features Applications Installation Guide Software Overview...

Page 10: ...PCIE 1744 is up to 30 MS s 1 1 Features The PCIE 1744 offers the following main features 32 bit PCI Express bus Mastering DMA data transfer Four A D converters for simultaneous sampling 12 bit A D co...

Page 11: ...ets you sample simultaneously 1 1 3 Supports S W Internal External Pacer Triggering The PCIE 1744 supports three kinds of trigger modes for A D conver sion software triggering internal pacer triggerin...

Page 12: ...anion CD ROM Wiring cables PCL 10901 1 PCL 1010B 1 optional Wiring board ADAM 3909 optional Computer Personal computer or workstation with a PCI Express bus slot running Windows 2000 XP or Vista Some...

Page 13: ...5 Chapter1 Figure 1 1 Installation Flow Chart...

Page 14: ...OM It also comes with all Advantech DA C cards Advantech s device drivers feature a complete I O function library to help boost your application performance The Advantech Device Drivers for Windows 98...

Page 15: ...ch offers a Tutorial Chapter in the Device Drivers Manual for your reference Please refer to the corresponding sections in this chapter of the Device Drivers Manual to begin your programming efforts Y...

Page 16: ...surement Function Alarm Function Communication port Function High speed Function Hardware Function For the usage and parameters of each function please refer to the Func tion Description chapter in th...

Page 17: ...ch as external triggers and or clock signals PCL 1010B 1 is designed for connecting to a signal source The cable links the PCIE 1744 with the signal source via the BNC connectors There are four BNC po...

Page 18: ...PCIE 1744 User Manual 10...

Page 19: ...es a package item checklist proper instructions about unpacking and step by step procedures for both driver and card installation Sections include Unpacking Driver Installation Hardware Installation D...

Page 20: ...the anti static bag to a metal part of your computer chassis before opening the bag Hold the card only by the metal bracket when removing it from the bag After taking out the card you should first ins...

Page 21: ...ckage Please follow the steps below to install the driver software Step 1 Insert the companion CD ROM into your CD ROM drive Step 2 The Setup program will be launched automatically if you have the AUT...

Page 22: ...he installation instruc tions step by step to complete your device driver setup Figure 2 2 Different Options for Driver Setup For further information on driver related issues an online version of the...

Page 23: ...dges and carefully align it with the slot Insert the card firmly into place Use of excessive force must be avoided or the card might be damaged 6 Fasten the bracket of the PCIE 1744 on the back panel...

Page 24: ...ager which was installed on your system during driver setup A complete device installation procedure should include board selection and device setup The following sections will guide you through the b...

Page 25: ...grams Advantech Automation Device Manager Advan tech Device Manager 2 You can then view the device s already installed on your system if any in the Installed Devices list box Figure 2 4 Device Manager...

Page 26: ...input tab functions on the other tabs are not supported for this model 2 5 1 Testing the Analog Input Function Make sure the Analog Input tab is selected otherwise click on the Ana log Input tab to br...

Page 27: ...19 Chapter2 Figure 2 6 Analog Input tab on the Device Test dialog box...

Page 28: ...PCIE 1744 User Manual 20...

Page 29: ...TER 3 Signal Connections This chapter provides information about how to connect input signals to the PCIE 1744 via the I O connectors Sections include Overview Switch and Jumper Settings Signal Connec...

Page 30: ...receiving data cor rectly A good signal connection can avoid unnecessary and costly dam age to your PC and other hardware devices This chapter provides useful information about how to connect input s...

Page 31: ...ble If there are multiple identical cards in the same chassis the BoardID switch helps differentiate the boards by identifying each card s device number with the switch setting The BoardID switch s un...

Page 32: ...lect JP2 to JP5 Use JP2 to JP5 to set input terminator values for each AI channel CH0 to CH3 JP1 Power on configuration after hot reset Keep the hardware register setting after hot reset Load the hard...

Page 33: ...are analog input connectors J1 is for AI0 J2 is for AI1 J3 is for AI2 and J4 is for AI3 Table 3 1 PS 2 Pin Assignments Pin Description 1 EXT TRIG 0 2 NC 3 EXT CLK 0 4 GND 5 EXT CLK 0 6 EXT CLK 1 Tabl...

Page 34: ...PCIE 1744 User Manual 26...

Page 35: ...R 4 Operation This chapter describes the following features of the PCIE 1744 card Analog input ranges and gains Analog input acquisition modes A D sample clock sources Trigger sources Analog Input Dat...

Page 36: ...er to Appendix C 4 AI Range Control 4 2 Analog Input Acquisition Modes The PCIE 1744 can acquire data in single value pacer post trigger delay trigger about trigger and pre trigger acquisition modes T...

Page 37: ...for analog input to prevent data loss 4 2 3 Post Trigger Acquisition Mode Post trigger allows you to acquire data based on a trigger event Posttrig ger acquisition starts when the PCIE 1744 detects t...

Page 38: ...hen the PCIE 1744 detects the trigger event and stop when the specified number of A D samples has been acquired or when you stop the operation This triggering mode must work with the DMA data transfer...

Page 39: ...fic sample number M after the trigger event The range of pre set sample number is from 2 to 65536 samples In about trigger mode users must first designate the size of the allocated memory and the amou...

Page 40: ...sition Mode has been set The sample clock source and sample rate The trigger source Assume the total acquired sample number is N then set the total sample number to be N 2 Figure 4 4 Pre Trigger Acqui...

Page 41: ...600 kHz This consideration can avoid an error condi tion often know as aliasing in which high frequency input components appear erroneously as lower frequencies when sampling 4 3 2 External A D Sample...

Page 42: ...ter issues a write to the board to begin acquisitions When you write the value to analog input trigger flag TRGF on Write BASE Eh to produce either a rising edge or falling edge trigger depend ing upo...

Page 43: ...ernal device to one of the four BNC source connec tors Which one of the four sources is selected as the trigger source can be defined or identified by writing to or reading from the flags from TS0 to...

Page 44: ...4 2 Analog Input Data Format A D Code Mapping Voltage Hex Dec 000h 0d FS 7FFh 2047d 1 LSB 800h 2048d 0 FFFh 2095d FS 1 LSB 1LSB FS 2048 Table 4 3 Corresponding Full Scale Values for Various Input Vol...

Page 45: ...2 CHAPTER 5 Calibration This chapter offers you a brief guide to the calibration procedure Sections include Calibration Procedure...

Page 46: ...es will show how it is done To perform an effective calibration prepare a standard 4 1 2 digits reso lution stable and low noise DC voltage source It is important as the accuracy of the device will de...

Page 47: ...indow will pop up Figure 5 2 Click the Calibration Button to Launch the Calibration Step 4 Follow the instruction of Calibration Wizard to input a correct DC voltage as a reference and click the Next...

Page 48: ...The Adjustment Process of Offset Calibration Step 6 If the reference DC voltage source and the wiring are both correct the calibration will proceed automatically after the Start button is clicked Whe...

Page 49: ...ncel button to stop the calibration Figure 5 6 Offset Calibration Failed Step 7 If the offset calibration is completed it will proceed to the Gain Calibration The steps of gain calibration are quite s...

Page 50: ...t gain calibration Note that the Sta tus will indicate Unknown as default at the beginning Figure 5 8 The Adjustment Process of Gain Calibration Step 9 When the gain calibration is completed click the...

Page 51: ...ure or click the Cancel button to stop the calibration Figure 5 10 Gain Calibration Failed Step 10 When the current channel is calibrated click the Finish button to end the procedure You can proceed t...

Page 52: ...PCIE 1744 User Manual 44...

Page 53: ...2 APPENDIX A Specifications...

Page 54: ...I 1 PS2 connector for ext clock and trigger Dimensions 175 mm x 100 mm 6 9 x 3 9 Power Consumption Typical 5 V 850 mA 12 V 600 mA Max 5 V 1 A 12 V 700mA Temperature Operating 0 70 C 32 158 F Storage 2...

Page 55: ...rigger pre trigger delay trigger about trigger Accuracy D C DNLE 1LSB No Missing Codes 12 Bits Guaranteed INLE 2LSB Offset error Adjustable to 1LSB Gain error Adjustable to 1LSB A C SINAD S N D 66 dB...

Page 56: ...PCIE 1744 User Manual 48...

Page 57: ...2 APPENDIX B Block Diagram...

Page 58: ...PCIE 1744 User Manual 50 Appendix B Block Diagram...

Page 59: ...2 APPENDIX C Register Structure Format...

Page 60: ...tions is provided only for users who would like to do their own low level programming C 2 Register Format The register format is the basis to control the PCIE 1744 There are some rules for programmer...

Page 61: ...nel 1 Single Value Acquisition R AI Channel 1 Data TRGF OV G1 G0 AD 11 AD 10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 4h W AI Channel 2 Single Value Acquisition R AI Channel 2 Data TRGF OV G1 G0 AD 11...

Page 62: ...FF FIF O1_ HF FIF O1_ EF FIF O0_ AF FIF O0_ AE FIFO 0_FF FIFO0_ HF FIFO 0_EF 12h W FIFO Control Register FRS T3 FCL R3 FRST2 FCL R2 R FIFO Status Register FIFO 3_AF FIF O3_ AE FIF O3_ FF FIF O3_ HF F...

Page 63: ...PF3 PF2 PF1 PF0 1Ch W DMA Counter Register CN 15 CN 14 CN1 3 CN1 2 CN 11 CN1 0 CN9 CN8 CN 7 CN 6 CN5 CN4 CN3 CN2 CN1 CN0 R CN 15 CN 14 CN1 3 CN1 2 CN 11 CN1 0 CN9 CN8 CN 7 CN 6 CN5 CN4 CN3 CN2 CN1 CN...

Page 64: ...voltage Register AT 7 AT 6 AT 5 AT 4 AT 3 AT2 AT1 AT0 26h W N A R N A 28h W Calibration Command Register CG1 CG0 X CM 2 CM 1 CM 0 CD 7 CD 6 CD 5 CD 4 CD 3 CD2 CD1 CD0 R CG 1 CG0 CBU SY CM 2 CM 1 CM 0...

Page 65: ...1744 Register Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 30h W Reset start read channel to CH0 R AD Channel n DATA TR GF OV G1 G0 AD1 1 AD1 0 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 32h W N A R AD C...

Page 66: ...g indicates whether a trigger event has happened during A D conversion process 2h W AI Channel 1 Single Value Acquisition R AI Channel 1 Data TR GF OV G1 G0 AD 11 AD 10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2...

Page 67: ...purposes Table C 6 Register for Analog Input Range Control Base Address HEX PCIE 1744 Register Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 8h W AI Range Control Register CH3 _G1 CH3 _G0 CH2 _G1 CH2 _...

Page 68: ...feed to the A D converters Table C 8 Register for Clock Source and Divider Base Address HEX PCIE 1744 Register Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Ch W Clock Source and Divider Register CKS...

Page 69: ...at 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Eh W Trigger Mode and Source Register TR GF DM A_T CF TSE TS2 TS1 TS0 TM2 TM1 TM0 R TR GF DM A_T CF TSE TS2 TS1 TS0 TM2 TM1 TM0 TM2 TM1 TM0 Meaning 0 0 0 Singl...

Page 70: ...0 12 FCLRn n 0 3 FIFO Clear register Write 1 to this bit to clear FIFO data FRSTn n 0 3 FIFO Reset register Write 1 to this bit to clear FIFO data and reset the AE and AF flag posi tion to 7FH Table C...

Page 71: ...is almost empty 0 FIFO is not almost empty FIFOn_AF n 0 3 FIFO Almost Full flag 1 FIFO is almost full 0 FIFO is not almost full Table C 11 Register for FIFO Status Base Address HEX PCIE 1744 Register...

Page 72: ...ormat 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 14h W FIFO 0 Programmable Flag Register PF14 PF13 FP12 PF11 PF10 PF9 PF8 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 R FIFO 0 Programmable Flag Register PF14 PF13 FP12...

Page 73: ...or delay trigger data counts after the trigger event Rest DMA Counter Before start the DMA counter write the BASE 1Eh to reset the DMA counter Table C 13 Register for DMA Counter Base Address HEX PCIE...

Page 74: ...Almost Full FIFO2_HFFIFO 2 Half Full FIFO2_AFFIFO 2 Almost Full FIFO3_HFFIFO 3 Half Full FIFO3_AFFIFO 3 Almost Full DMA_TCDMA counter Terminal Count INTE Total Interrupt Enable C 12 2 Interrupt Flag...

Page 75: ...Half Full interrupt flag INTF5 FIFO 2 Almost Full interrupt flag INTF6 FIFO 3 Half Full interrupt flag INTF7 FIFO 3 Almost Full interrupt flag INTF8 DMA counter Terminal Count interrupt flag INTF Tota...

Page 76: ...hreshold Voltage Base Address HEX PCIE 1744 Register Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 24h W Analog Trigger Threshold voltage Register AT7 AT6 AT5 AT4 AT3 AT2 AT1 AT0 R Analog Trigger Thres...

Page 77: ...10 9 8 7 6 5 4 3 2 1 0 28h W Calibration Command Register CG1 CG0 X CM2 CM1 CM0 CD 7 CD 6 CD 5 CD 4 CD3 CD2 CD1 CD0 R CG1 CG0 CBU SY CM2 CM1 CM0 CD 7 CD 6 CD 5 CD 4 CD3 CD2 CD1 CD0 CM2 CM1 CM0 Meanin...

Page 78: ...A transfer data from CH0 Before start DMA transfer user has to reset the start channel to CH0 This only for four channels DMA data transfer Table C 18 Register for BoardID Switch Base Address HEX PCIE...

Page 79: ...port 1 2 or 4 channels data acquisition For 1 channel data acquisition only channel 0 or 2 is acceptable For 2 channels data acquisition only channel 0 1 or 2 3 is acceptable The DMA data transfer to...

Page 80: ...REQ 0 FIFO 0 flag 1 FIFO 2 flag Memory Address D31 D16 D15 D0 N CH1 data 0 CH0 data 0 N 1 CH1 data 1 CH0 data 1 N 2 CH1 data 2 CH0 data 2 N 3 CH1 data 3 CH0 data 3 Memory Address D31 D16 D15 D0 N CH1...

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