PCIE-1744 User Manual
60
C.6 Clock Source and Divider- Write/Read BASE+C
DIV7: DIV0
Clock Divider
When select the internal clock source (60MHz) the clock will pre-divide
by the clock divider. The divider is 8-bit wide, so it could divide from 2 to
256.
CKS1: CKS0
Clock Source selector
These 2 bits select the clock source feed to the A/D converters.
Table C.8: Register for Clock Source and Divider
Base
Address
+ HEX
PCIE-1744 Register Format
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Ch W Clock Source and Divider Register
CKS
1
CKS
0
DIV
7
DIV
6
DIV
5
DIV
4
DIV
3
DIV
2
DIV
1
DIV
0
R
CKS
1
CKS
0
DIV
7
DIV
6
DIV
5
DIV
4
DIV
3
DIV
2
DIV
1
DIV
0
DIV7: DIV0 Divide value
00h
N/A
01h
divide by 2
02h
divide by 3
.
.
FEh
divide by 255
FFh
divide by 256
CKS1
CKS0
Clock source
0
0
Internal clock 60MHz
0
1
External clock 0
1
0
External clock 1
1
1
Off
Summary of Contents for PCIE-1744
Page 1: ...PCIE 1744 30 MS s Simultaneous 4 ch Analog Input PCI Express Card User Manual...
Page 13: ...5 Chapter1 Figure 1 1 Installation Flow Chart...
Page 18: ...PCIE 1744 User Manual 10...
Page 27: ...19 Chapter2 Figure 2 6 Analog Input tab on the Device Test dialog box...
Page 28: ...PCIE 1744 User Manual 20...
Page 34: ...PCIE 1744 User Manual 26...
Page 52: ...PCIE 1744 User Manual 44...
Page 53: ...2 APPENDIX A Specifications...
Page 56: ...PCIE 1744 User Manual 48...
Page 57: ...2 APPENDIX B Block Diagram...
Page 58: ...PCIE 1744 User Manual 50 Appendix B Block Diagram...