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PCI-1713 User's Manual

Summary of Contents for PCI-1713

Page 1: ...PCI 1713 32 channel Isolated Analog Input Card User s manual ...

Page 2: ... rights of third parties which may result from its use Acknowledgments PC LabCard is a trademark of Advantech Co Ltd IBM and PC are trademarks of International Business Machines Corporation MS DOS and Windows are trademarks of Microsoft Corporation Intel and Pentium are trademarks of Intel Corporation CE notification The PCI 1713 developed byADVANTECH CO LTD has passed the CE test for environmenta...

Page 3: ... 2 2 Unpacking 8 2 3 Installation Instructions 9 CHAPTER 3 Signal Connections 11 3 1 Overview 12 3 2 I O Connector 12 3 3 Analog Input Connections 14 3 4 Field Wiring Considerations 17 CHAPTER 4 Register Structure and Format 19 4 1 Overview 20 4 2 I O Port Address Map 20 4 3 A D Data 23 4 4 Software A D Trigger 23 4 5 A D Channel Range Setting 23 4 6 MUX Control 25 ...

Page 4: ...3 A D Calibration 33 APPENDIX A 82C54 Counter Chip Functions 35 A 1 Introduction 36 A 2 Counter Read Write and Control Registers 36 A 3 Counter Operating Modes 39 A 4 Counter Operations 41 APPENDIXB PCLD 881BWiringTerminalBoard 43 B 1 Introduction 44 B 2 Features 44 B 3 Application 44 B 4 Board Layout 45 B 5 Single ended Connections 46 B 6 Differential Connections 47 B 7 Technical Diagram 48 ...

Page 5: ...Chapter 1 General Information 1 1 General Information C H A P T E R ...

Page 6: ...ues and configurations for each channel This design lets you perform multi channel sampling with different gains for each channel and with free combination of single ended and differential inputs High speed Data Acquisition The PCI 1713 provides a sampling rate up to 100k samples s It has an on board FIFO buffer which can store up to 4K A D samples and generates an interrupt signal when the FIFO i...

Page 7: ...el of isolation protection for their data acquisition system 1 2 Features 32 single ended or 16 differential analog inputs or a combina tion 12 bit A D converter with up to 100 kHz sampling rate Programmable gain for each input channel Automatic channel gain scanning On board 4K samples FIFO buffer Programmable pacer 1 3 Specifications Analog Input Channels 32 single ended or 16 differential softw...

Page 8: ... of FSR 1LSB 8 0 04 of FSR 1LSB Linearity error 1LSB Drift Typical 30 PPM C 0 60 C Inputimpedance 1GΩ Trigger mode Software on board programmable pacer or external Trigger Input TTL level Programmable Timer Counter Counter chip 82C54 or equivalent Counters 3 channels 16 bits 2 channels are permanently configured as programmable pacers 1 channel is un used Time base Channel 1 10 MHz Channel 2 Takes...

Page 9: ...mensions 175mmx100mm 6 9 x3 9 Powerconsumption 5V 850 mA Typical 5 V 1 0 A Max Operating temperature 0 60 C 32 140 F refer to IEC 68 2 1 2 Storage temperature 20 70 C 4 158 F Operating humidity 5 95 RH non condensing refer to IEC 68 2 3 MTBF over 85 310 hrs 25 C grounded fixed environment ...

Page 10: ...n Isolation PCI Target Controller Address Bus Address Decoder 10 MHz OSC Counter 1 Counter 2 Pacer Gain Code Generator ADC Control Logic Channel Code Generator Multiplexer 32 S E or 16 Diff PGIA Isolation EXT_TRG Data Bus INT INT Generator PCI B us 12 bit A D Converter AI 0 AI 1 AI31 Channel Code ...

Page 11: ...Chapter 2 Installation 7 2 Installation C H A P T E R ...

Page 12: ...angements to repair or replace the unit 2 2 Unpacking The PCI 1713 contains components that are sensitive and vulnerable to static electricity Discharge any static electricity on your body to ground by touching the back of the system unit grounded metal before you touch the board Remove the PCI 1713 card from its protective packaging by grasping the card s rear panel Handle the card only by its ed...

Page 13: ...omputer 4 Select an empty 5 V PCI slot Remove the screw that secures the expansion slot cover to the system unit Save the screw to secure the interface card retaining bracket 5 Carefully grasp the upper edge of the PCI 1713 Align the hole in the retaining bracket with the hole on the expansion slot and align the gold striped edge connector with the expansion slot socket Press the card into the soc...

Page 14: ...1 0 PCI 1713 User s Manual ...

Page 15: ...Chapter 3 Signal Connections 11 3 Signal Connections C H A P T E R ...

Page 16: ...r The I O connector for the PCI 1713 card is a 37 pin D type connector which you can connect to 37 pin D type accessories with Advantech s PCL 10137 cable Note The PCI 1713 does not include the PCL 10137 cable assembly The following figure shows the pin assignments for the 37 pin I O connector on the PCI 1713 card Figure 3 1 I O connector pin assignments for the PCI 1713 card 1 2 20 3 4 5 6 7 8 9 ...

Page 17: ... i 0 2 4 30 can be configured as either two single ended inputs or one differential input GND Ground These pins are the reference points for single ended measurements and the bias current return point for differential measurement EXT_TRG GND Input A D External Trigger This pin is the external trigger signal input for the A D conversion A low to high edge triggers A D conversion to happen ...

Page 18: ...common ground A signal source without a local ground is also called a floating source It is fairly simple to connect a single ended channel to a floating signal source In this mode the PCI 1713 card provides a reference ground for external floating signal sources Figure 3 2 shows a single ended channel connection between a floating signal source and an input channel on the PCI 1713 card Figure 3 2...

Page 19: ...nected through the ground return of the equipment and building wiring The difference between the ground voltages forms a common mode voltage Vcm To avoid the ground loop noise effect caused by common mode voltages you can connect the signal ground to the Low input Figure 3 3 shows a differential channel connection between a ground referenced signal source and an input channel on the PCI 1713 card ...

Page 20: ...ial channel connection between a floating signal source and an input channel on the PCI 1713 card In this figure each side of the floating signal source is connected through a resistor to the AIGND This connection can reject the common mode voltage between the signal source and the PCI 1713 card ground Figure 3 4 Differential input channel connection floating signal source ra rb External Internal ...

Page 21: ...u don t provide any protection The following suggestions will be helpful when running signal wires between signal sources and the PCI 1713 card Please make sure that you have carefully routed signal cables to the card You must separate the cabling from noise sources Try to keep video monitors far away from the analog signal cables because these are a common noise source in a PCI data acquisition s...

Page 22: ...Also keep your signals far from electric motors breakers or welding equipment as these can create magnetic fields Keep a reasonable distance between high voltage or high current lines and signal cables connected to the PCI 1713 card if the cables run parallel or route signal cables at right angles to high voltage current cables ...

Page 23: ...Chapter 4 Register Structure and Format 19 4 Register Structure and Format C H A P T E R ...

Page 24: ... PCI 1713 card at a register level is to understand the function of the card s registers The information in the following sections is provided only for users who would like to do their own low level programming 4 2 I O Port Address Map The PCI 1713 card requires 18 addresses in the PC s I O space The address of each register is specified as an offset from the card s base address For example BASE 0...

Page 25: ... 5 4 3 2 1 0 Channel Number and A D Data 1 AD11 AD10 AD9 AD8 0 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 N A 3 2 N A 5 4 Status Register 7 IRQ F F F H F E 6 ONE FH IRQEN GATE EXT PACER SW N A 9 8 Counter 0 25 24 D7 D6 D5 D4 D3 D2 D1 D0 Counter 1 27 26 D7 D6 D5 D4 D3 D2 D1 D0 Counter 2 29 28 D7 D6 D5 D4 D3 D2 D1 D0 N A 31 30 ...

Page 26: ...Range Setting 3 2 S D B U G2 G1 G0 MUX Control 5 Stop channel 4 Start channel Control Register 7 6 ONE FH IRQ GATE EXT PACER SW Clear Interrupt and FIFO 9 clear FIFO 8 clear interrupt Counter 0 25 24 D7 D6 D5 D4 D3 D2 D1 D0 Counter 1 27 26 D7 D6 D5 D4 D3 D2 D1 D0 Counter 2 29 28 D7 D6 D5 D4 D3 D2 D1 D0 Counter Control 31 30 D7 D6 D5 D4 D3 D2 D1 D0 ...

Page 27: ...al pulse Bit 2 to bit 0 of register BASE 6 can select the trigger source see page 27 and page 28 for the register layout of BASE 6 and programming information If you select software triggering a write to the register BASE 0 with any value will trigger an A D conversion 4 5 A D Channel Range Setting BASE 2 Each A D channel has its own input range controlled by a range code stored in the on board RA...

Page 28: ...ollowing table lists the gain codes for the PCI 1713 Table 4 4 Gain codes for the PCI 1713 Write A D channel range setting Bit 7 6 5 4 3 2 1 0 BASE 2 S D B U G2 G1 G0 PCI 1713 Input Range V Gain B U Gain Code G2 G1 G0 5 to 5 1 0 0 0 0 2 5 to 2 5 2 0 0 0 1 1 25 to 1 25 4 0 0 1 0 0 625 to 0 625 8 0 0 1 1 10 to 10 0 5 0 1 0 0 N A 0 1 0 1 N A 0 1 1 0 N A 0 1 1 1 0 to 10 1 1 0 0 0 0 to 5 2 1 0 0 1 0 to...

Page 29: ...uously scan between channels and the range setting may be set to an unexpected channel Make sure the A D trigger source is turned off to avoid this kind of error The write only registers of BASE 4 and BASE 5 control how the multiplexers MUXs scan BASE 4 bit 4 to bit 0 CL4 CL0 hold the start scan channel number and BASE 5 bit 4 to bit 0 CH4 CH0 hold the stop scan channel number Writing to these two...

Page 30: ...is set as differential then channel 0 and channel 1 are combined into one channel and refer to the gain code and B U of channel 0 the channel 1 values are unavailable By the same rule if channel 2 is set as differential then channel 2 and channel 3 are combined into one channel and refer to the gain code and B U of channel 2 the channel 3 values are unavailable The following examples show the scan...

Page 31: ...0 to disable EXT External trigger enable bit Set 1 to enable external trigger and set 0 to disable Note Users cannot enable SW PACER and EXT concurrently GATE External trigger gate function enable bit Set 1 to enable external trigger gate function and set 0 to disable IRQEN Interrupt enable bit Set 1 to enable interrupt and set 0 to disable ONE FH Interrupt source bit Set 0 to interrupt when an A ...

Page 32: ...mpty flag This bit indicates whether the FIFO is empty 1 means that the FIFO is empty F H FIFO Half full flag This bit indicates whether the FIFO is half full 1 means that the FIFO is half full F F FIFO Full flag This bit indicates whether the FIFO is full 1 means that the FIFO is full IRQ Interrupt flag This bit indicates the interrupt status 1 means that an interrupt has occurred Read Status Reg...

Page 33: ...rogrammable Timer Counter Registers BASE 24 BASE 26 BASE 28 and BASE 30 The four registers of BASE 24 BASE 26 BASE 28 and BASE 30 are used for the 82C54 programmable timer counter Please refer to Appendix A data sheets for detailed application information Note Users have to use a 16 bit word command to read write each register Write Clear Interrupt and FIFO Bit 7 6 5 4 3 2 1 0 BASE 9 Clear FIFO BA...

Page 34: ...30 PCI 1713 User s Manual ...

Page 35: ...Chapter 5 Calibration 31 5 Calibration C H A P T E R ...

Page 36: ...rocedure with a variety of prompts and graphic displays showing you all of the correct settings and adjustments This chapter offers a brief guide to these calibration programs To perform a satisfactory calibration you need a 41 2 digit digital multimeter and a voltage calibrator or a stable noise free D C voltage source 5 2 VR Assignment There are four variable resistors VRs on the PCL 1713 card T...

Page 37: ...The basic steps are outlined below 1 Set analog input channel AI0 as single ended bipolar range 5 V and connect to the ground 2 ReadTP1 asVG1 3 Change AI0 range to 0 625 V and read TP1 as VG8 4 AdjustVR4 until 0 05 mV VG1 VG8 0 05 mV 5 Repeat steps 1 4 until ther is no more need to adjust VR4 6 Set analog input channel AI0 as single ended bipolar range 5 V and set AI1 as single ended unipolar rang...

Page 38: ...10 adjusting VR2 and VR1 12 Connect a DC voltage source with value equal to 2047 5 LSB 4 9959V toAI1 13 Adjust VR3 until the output codes from the card s AI1 flickers between 2047 and 2048 A D code Mapping Voltage Hex Dec Bipolar 5V Unipolar 0 to 10V 000h 0 4 9971V 0V 7FFh 2047 0 0024V 4 9947V 800h 2048 0V 4 9971V FFFh 4095 4 9947V 9 9918V ...

Page 39: ...Appendix A 8524 Counter Chip Functions 35 A 82C54 Counter Chip Functions A P P E N D I X ...

Page 40: ...terval timer uses four registers at address es BASE 24 Dec BASE 26 Dec BASE 28 Dec and BASE 30 Dec for read write and control of counter functions Register functions appear below Register Function BASE 24 Dec Counter 0 read write BASE 26 Dec Counter 1 read write BASE 28 Dec Counter 2 read write BASE 30 Dec Counter control word Since the 82C54 counter uses a 16 bit structure each section of read wr...

Page 41: ...te LSB 0 1 Read write MSB 1 0 Read write LSB first 1 1 then MSB M2 M1 M0 Select operating mode M2 M1 M0 Mode Description 0 0 0 0 Stop on terminal count 0 0 1 1 Programmable one shot X 1 0 2 Rate generator X 1 1 3 Square wave rate generator 1 0 0 4 Software triggered strobe 1 0 1 5 Hardware triggered strobe BCD Select binary or BCD counting B C D Type 0 Binary counting 16 bits 1 Binary coded decima...

Page 42: ... CNT 0 Latch count of selected counter s STA 0 Latch status of selected counter s C2 C1 C0 Select counter for a read back operation C2 1 select Counter 2 C1 1 select Counter 1 C0 1 select Counter 0 If you set both SC1 and SC0 to 1 and STA to 0 the register selected by C2 to C0 contains a byte which shows the status of the counter The data format of the counter read write register then becomes BASE...

Page 43: ...then go high on the terminal count If you load a new count value while the output is low the new value will not affect the duration of the one shot pulse until the succeeding trigger You can read the current count at any time without affecting the one shot pulse The one shot is retriggerable thus the output will remain low for the full count after any rising edge at the gate input MODE 2 Rate Gene...

Page 44: ... and the full count is reloaded The first clock pulse following the reload decrements the counter by 3 Subsequent clock pulses decre ment the count by two until time out then the whole process is repeated In this way if the count is odd the output will be high for N 1 2 counts and low for N 1 2 counts MODE 4 Software Triggered Strobe After the mode is set the output will be high When the count is ...

Page 45: ... by MSB It is important that you make your read write operations in pairs and keep track of the byte order Counter Read back Command The 82C54 counter read back command lets you check the count value programmed mode and current states of the OUT pin and Null Count flag of the selected counter s You write this command to the control word register Format is as shown at the beginning of this section ...

Page 46: ...ports the counter latch operation in two ways The first way is to set bits RW1 and RW0 to 0 This latches the count of the selected counter in a 16 bit hold register The second way is to perform a latch operation under the read back command Set bits SC1 and SC0 to 1 and CNT 0 The second method has the advantage of operating several counters at the same time A subsequent read operation on the select...

Page 47: ...Appendix B PCLD 881B Wiring Terminal Board 43 B PCLD 881B Wiring Terminal Board A P P E N D I X ...

Page 48: ...apacitors on to the board s circuit pads B 2 Features Low cost screw terminal board for the PCI 1713 and PCL 813B with 37 pin D type connector 40 terminal points for one 37 pin D type port Reserved space for signal conditioning circuits such as low pass filter voltage attenuator and current shunt Industrial type termination blocks permit heavy duty and reliable signal connections Table top mountin...

Page 49: ...t the upper two pins of JP1 to connect pin 1 of CN4 to ground or short the lower two pins of JP1 to float pin 1 of CN4 for connection to an external trigger source However when configuring for the PCL 813B the user has to short the upper two pins of JP1 because no external trigger is supported PCLD 881B Rev A1 01 1 AI 0 AI 1 AI 2 AI 3 AI 4 AI 5 AI 6 AI 7 GND GND AI 8 AI 9 AI10 AI11 AI12 AI13 AI14 ...

Page 50: ...dB c 10 1 voltage attenuator RAn 9 kΩ RBn 1 kΩ Cn none Attenuation d 4 20 mA to 1 5 VDC signal converter RAn 0 Ω short RBn 250 Ω 0 1 precision resistor Cn none RBn RAn RBn 1 2πRAnCn AIn AIGND Internal side Field side RAn RBn Cn where n 0 1 2 31 AIn GND Internal side Field side AIn GND Internal side Field side RBn AIn GND Internal side Field side RAn Cn AIn GND Internal side Field side RAn RBn ...

Page 51: ...e attenuator RAn 4 5 kΩ RAn 1 4 5 kΩ RDn 1 kΩ Cn none Attenuation d 4 20 mA to 1 5 VDC signal converter RAn 0 Ω short RAn 1 0 Ω short RDn 250 Ω 0 1 precision resistor CDn none AIn AIn 1 Internal side Field side AIn AIn 1 Internal side Field side RAn RDn RAn 1 AIn AIn 1 Internal side Field side RAn CDn RAn 1 1 2π RAn RAn 1 CDn RDn RAn RAn 1 RDn where n 0 2 4 30 AIn AIn 1 Internal side Field side RA...

Page 52: ... C 13 C D 12 R D 12 R A 14 R A 15 R B 15 R B 14 C 14 C 15 C D 14 R D 14 R A 16 R A 17 R B 17 R B 16 C 16 C 17 C D 16 R D 16 R A 18 R A 19 R B 19 R B 18 C 18 C 19 C D 18 R D 18 R A 20 R A 21 R B 21 R B 20 C 20 C 21 R D 20 R A 22 R A 23 R B 23 R B 22 C 22 C 23 R D 22 R A 24 R A 25 R B 25 R B 24 C 24 C 25 C D 24 R D 24 R A 26 R A 27 R B 27 R B 26 C 26 C 27 C D 26 R D 26 R A 28 R A 29 R B 29 R B 28 C ...

Page 53: ...4 32 13 31 12 30 11 29 10 28 9 27 8 26 7 25 6 24 5 23 4 22 3 21 2 20 1 39 38 A I6 A I5 A I4 A I3 A I2 A I1 A I0 A I1 3 A I1 2 A I1 1 A I1 0 A I9 A I8 A I7 A I1 6 A I1 5 A I1 4 A I2 3 A I2 2 A I2 1 A I2 0 A I1 9 A I1 8 A I1 7 A I3 0 A I2 9 A I2 6 A I2 5 A I2 4 E X T _ T R G A I3 1 A I2 8 A I2 7 G N D G N D G N D G N D E X T _ T R G ...

Page 54: ...50 PCI 1713 User s Manual ...

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