Advantech PCI-1713, User Manual

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Appendix A 8524 Counter Chip Functions 39
A.3 Counter Operating Modes
MODE 0 – Stop on Terminal Count
The output will initially be low after you set this mode of operation.
After you load the count into the selected count register, the output
will remain low and the counter will count. When the counter reaches
the terminal count, its output will go high and remain high until you
reload it with the mode or a new count value. The counter continues
to decrement after it reaches the terminal count. Rewriting a counter
register during counting has the following results:
1. Writing to the first byte stops the current counting.
2. Writing to the second byte starts the new count.
MODE 1 – Programmable One-shot Pulse
The output is initially high. The output will go low on the count
following the rising edge of the gate input. It will then go high on the
terminal count. If you load a new count value while the output is low,
the new value will not affect the duration of the one-shot pulse until
the succeeding trigger. You can read the current count at any time
without affecting the one-shot pulse. The one-shot is retriggerable,
thus the output will remain low for the full count after any rising edge
at the gate input.
MODE 2 – Rate Generator
The output will be low for one period of the input clock. The period
from one output pulse to the next equals the number of input counts in
the counter register. If you reload the counter register between output
pulses, the present period will not be affected, but the subsequent
period will reflect the value.
The gate input, when low, will force the output high. When the gate
input goes high, the counter will start from the initial count. You can
thus use the gate input to synchronize the counter.
With this mode the output will remain high until you load the count
register. You can also synchronize the output by software.